公开(公告)号：US07830289B2

公开(公告)日：2010-11-09

申请号：US12247330

申请日：2008-10-08

Applicant: Simone Ferri

Inventor： Simone Ferri

IPC: H03M3/00

CPC classification number: H03M3/412 ,  H03M3/328 ,  H03M3/432 ,  H03M7/3042

Abstract: The circuit includes, upstream from a PWM quantizer, that is between the output of the sigma-delta modulator and the input of the PWM or PWM-like quantizer, a second or ancillary sigma-delta stage of any order and architecture, with the function of controlling the minimum dynamic of the sigma-delta modulator. This second sigma-delta stage is input with the output signal of the sigma-delta modulator summed to a signal corresponding to the difference between the input signal and the output signal of the second sigma-delta stage, delayed by a delay block.

Abstract translation: 该电路包括在PWM量化器的上游，位于Σ-Δ调制器的输出端与PWM或类PWM量化器的输入端之间，任何阶数和结构的第二或辅助Σ-Δ级，具有功能 控制Σ-Δ调制器的最小动态。 输入第二Σ-Δ级，其中Σ-Δ调制器的输出信号相加到对应于输入信号和第二Σ-Δ级的输出信号之间的差的信号，延迟延迟块。

公开(公告)号：US20090096649A1

公开(公告)日：2009-04-16

申请号：US12247330

申请日：2008-10-08

Applicant: Simone FERRI

Inventor： Simone FERRI

IPC: H03M3/00

CPC classification number: H03M3/412 ,  H03M3/328 ,  H03M3/432 ,  H03M7/3042

Abstract: The circuit includes, upstream from a PWM quantizer, that is between the output of the sigma-delta modulator and the input of the PWM or PWM-like quantizer, a second or ancillary sigma-delta stage of any order and architecture, with the function of controlling the minimum dynamic of the sigma-delta modulator. This second sigma-delta stage is input with the output signal of the sigma-delta modulator summed to a signal corresponding to the difference between the input signal and the output signal of the second sigma-delta stage, delayed by a delay block.

Abstract translation: 该电路包括在PWM量化器的上游，位于Σ-Δ调制器的输出端与PWM或类PWM量化器的输入端之间，任何阶数和结构的第二或辅助Σ-Δ级，具有功能 控制Σ-Δ调制器的最小动态。 输入第二Σ-Δ级，其中Σ-Δ调制器的输出信号相加到对应于输入信号和第二Σ-Δ级的输出信号之间的差的信号，延迟延迟块。