Method for faster timing closure and better quality of results in IC physical design
    1.
    发明授权
    Method for faster timing closure and better quality of results in IC physical design 有权
    更快的时序关闭方法和更好的IC物理设计质量

    公开(公告)号:US07149992B2

    公开(公告)日:2006-12-12

    申请号:US10669496

    申请日:2003-09-23

    CPC classification number: G06F17/5031 G06F17/5068

    Abstract: A selective IPO procedure based on the concept of a “timing violation potential” prioritizes the components and nets in a critical path. User input criteria is used to select the components or nets (or both) which have the larger “timing violation potential;” only those components and nets are then operated on. After a selective IPO step, the total number of critical paths is reduced, as well as the worst negative slacks (WNS) of the critical path compared to the traditional IPO method.

    Abstract translation: 基于“定时违规潜力”概念的选择性IPO程序将组件和网络放在关键路径中。 用户输入标准用于选择具有较大“定时违规潜力”的组件或网络(或两者); 然后仅操作那些组件和网络。 在选择IPO步骤之后,与传统IPO方法相比,关键路径的总数减少,以及关键路径的最差负宽度(WNS)。

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