公开(公告)号：US07746180B2

公开(公告)日：2010-06-29

申请号：US12363156

申请日：2009-01-30

申请人： Shinichi Yamane ,  Seiji Wantanabe

发明人： Shinichi Yamane ,  Seiji Wantanabe

IPC分类号： H03L7/00

CPC分类号： H03L7/085 ,  H03L7/0807 ,  H03L7/087 ,  H03L7/0898 ,  H04L7/0087

摘要： This invention relates to a phase-locked loop circuit and a data reproduction apparatus, which can reduce a processing time that is required for initial adjustment in the data reproduction apparatus. In a digital data reproduction apparatus having two control functions, i.e., phase and duty adjustments for binarized data, the phase comparison with one edge is performed only at the phase adjustment by means of a phase-locked loop circuit 33 having an edge switching means 4 which controls the phase comparator 1. The phase comparator 1 inputs the binarized and a bit synchronous clock, and switches the output between a comparison result with one edge, i.e., a rising edge or a falling edge of binarized data, and a comparison result with both edges.

摘要翻译： 本发明涉及一种可以减少在数据再现装置中进行初始调整所需的处理时间的锁相环电路和数据再现装置。 在具有两个控制功能（即二进制数据的相位和占空比调整）的数字数据再现装置中，仅通过具有边沿切换装置4的锁相环电路33在相位调整时执行与一个边沿的相位比较 其控制相位比较器1.相位比较器1输入二进制和位同步时钟，并且在一个比较结果与一个边沿之间切换输出，即二值化数据的上升沿或下降沿，以及与 两边。