知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

5 条记录 (耗时 0.01 秒)

    Digital timing recovery method for communication receivers
    1.
    发明授权
    Digital timing recovery method for communication receivers 有权
    通信接收机的数字定时恢复方法

    公开(公告)号：US06983032B2

    公开(公告)日：2006-01-03

    申请号：US09941002

    申请日：2001-08-28

    申请人： Fernando A. Mujica ,  Udayan Dasgupta ,  Sandeep Kesrimal Oswal ,  Murtaza Ali ,  Pradeep Kiran Sarvepalli ,  Prakash Easwaran ,  Diptendra Narayan Basu

    发明人： Fernando A. Mujica ,  Udayan Dasgupta ,  Sandeep Kesrimal Oswal ,  Murtaza Ali ,  Pradeep Kiran Sarvepalli ,  Prakash Easwaran ,  Diptendra Narayan Basu

    IPC分类号： H03D3/24

    CPC分类号： H04L7/0337 ,  H04L27/2657

    摘要： The present invention provides an apparatus, system and method for synchronizing a local clock signal with a remote clock signal in a communication network. Phase information is used to calculate a number of “clock jitters” per unit of time needed to synchronize the locally generated clock with the remote clock. Introducing (removing) a given amount of delay at a particular point in the local clock signal results in a positive (negative) jitter in which its minimum value defines the jitter resolution. The jitters are introduced to the local clock signal from a plurality of tapped delay line elements (310) selected by a phase selector (350) in response to a timing correction signal issued by a phase error module (520).

    摘要翻译： 本发明提供了一种在本地时钟信号与通信网络中的远程时钟信号同步的装置，系统和方法。 相位信息用于计算在本地生成的时钟与远程时钟同步所需的每单位时间的“时钟抖动”数量。 在本地时钟信号的特定点引入（去除）给定量的延迟会导致正（负）抖动，其中最小值定义抖动分辨率。 响应于由相位误差模块（520）发出的定时校正信号，从由相位选择器（350）选择的多个抽头延迟线元件（310）中将抖动引入本地时钟信号。

    Hardware assisted automatic gain control for digital subscriber line modems
    2.
    发明授权
    Hardware assisted automatic gain control for digital subscriber line modems 有权
    数字用户线调制解调器的硬件辅助自动增益控制

    公开(公告)号：US06480068B1

    公开(公告)日：2002-11-12

    申请号：US09966055

    申请日：2001-09-28

    申请人： Fernando A. Mujica ,  Prakash Easwaran ,  Sandeep Kesrimal Oswal

    发明人： Fernando A. Mujica ,  Prakash Easwaran ,  Sandeep Kesrimal Oswal

    IPC分类号： H03G310

    CPC分类号： H03G3/3042

    摘要： The present invention provides a hardware assisted automatic gain control (AGC) for a communication network. A dedicated hardware portion of the AGC, which works in cooperation with software implemented functionality (400), is included to detect saturation conditions in the internal nodes of the analog front end (200) in which a plurality of gain stages (PGA1, PGA2, PGA3) and filter stages (H1, H2, H3) are interleaved with inaccessible intermediate points. The saturation detection logic includes a comparator (21, 22, 23) and flip-flop (27, 28, 29) for each gain stage (PGA1, PGA2, PGA3) and can be integrated directly in the analog front end 200. The dedicated hardware can further be included in a codec of a modem in a digital subscriber line (DSL) system.

    摘要翻译： 本发明提供了一种用于通信网络的硬件辅助自动增益控制（AGC）。 包括与软件实现的功能（400）协同工作的AGC的专用硬件部分，以检测模拟前端（200）的内部节点中的饱和状态，其中多个增益级（PGA1，PGA2， PGA3）和滤波器级（H1，H2，H3）与不可访问的中间点交错。 饱和检测逻辑包括用于每个增益级（PGA1，PGA2，PGA3）的比较器（21,22,23）和触发器（27,28,29），并且可以直接集成在模拟前端200中。专用 硬件可以进一步包括在数字用户线（DSL）系统中的调制解调器的编解码器中。