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    Complex phase-locked loop demodulator for low-IF and zero-IF radio receivers
    1.
    发明授权
    Complex phase-locked loop demodulator for low-IF and zero-IF radio receivers 有权
    用于低中频和零中频无线电接收机的复杂锁相环解调器

    公开(公告)号：US06785346B1

    公开(公告)日：2004-08-31

    申请号：US09676233

    申请日：2000-09-29

    申请人： Neil Birkett ,  Norm Filiol ,  Thomas Riley

    发明人： Neil Birkett ,  Norm Filiol ,  Thomas Riley

    IPC分类号： H03D318

    CPC分类号： H04L27/3836 ,  H03D3/245

    摘要： A digital demodulator which coherently demodulates a low-IF or zero-IF complex signal using a complex-valued phase-locked loop (CPPL). The CPPL includes a numerical controlled oscillator, four multipliers and two combiners to provide independent phase/frequency and amplitude outputs. The CPLL exhibits in first order PLL dynamics without a loop filter in the feedback loop to the NCO. However a filter with one or more poles may be included in the feedback circuit to exhibit 2nd or higher order PLL dynamics. The CPLL allows coherent demodulation of extremely low FM modulation indexes whereby the incoming frequency drift may be larger than the frequency deviation. It can also be used to coherently demodulate signals which have combined amplitude and phase characteristics.

    摘要翻译： 数字解调器，其使用复值锁相环（CPPL）相干地解调低中频或零中频复信号。 CPPL包括数控振荡器，四个乘法器和两个组合器，以提供独立的相位/频率和幅度输出。 CPLL在没有环路滤波器的一阶PLL动态中展现了到NCO的反馈环路。 然而，具有一个或多个极点的滤波器可以包括在反馈电路中以呈现2阶或更高阶PLL动力学。 CPLL允许相干解调极低的FM调制指数，从而输入频率漂移可能大于频率偏差。 它也可以用于相干解调具有组合幅度和相位特性的信号。

    Complex phase-locked loop demodulator for low-IF and zero-IF radio receivers
    2.
    发明授权
    Complex phase-locked loop demodulator for low-IF and zero-IF radio receivers 有权
    用于低中频和零中频无线电接收机的复杂锁相环解调器

    公开(公告)号：US07079598B2

    公开(公告)日：2006-07-18

    申请号：US10891586

    申请日：2004-07-15

    申请人： Neil Birkett ,  Norm Filiol ,  Thomas Riley

    发明人： Neil Birkett ,  Norm Filiol ,  Thomas Riley

    IPC分类号： H04B17/00

    CPC分类号： H04L27/3836 ,  H03D3/245

    摘要： A digital demodulator which coherently demodulates a low-IF or zero-IF complex signal using a complex-valued phase-locked loop (CPPL). The CPPL includes a numerical controlled oscillator, four multipliers and two combiners to provide independent phase/frequency and amplitude outputs. The CPLL exhibits in first order PLL dynamics without a loop filter in the feedback loop to the NCO. However a filter with one or more poles may be included in the feedback circuit to exhibit 2nd or higher order PLL dynamics. The CPLL allows coherent demodulation of extremely low FM modulation indexes whereby the incoming frequency drift may be larger than the frequency deviation. It can also be used to coherently demodulate signals which have combined amplitude and phase characteristics.

    摘要翻译： 数字解调器，其使用复值锁相环（CPPL）相干地解调低中频或零中频复信号。 CPPL包括数控振荡器，四个乘法器和两个组合器，以提供独立的相位/频率和幅度输出。 CPLL在没有环路滤波器的一阶PLL动态中展现了到NCO的反馈环路。 然而，具有一个或多个极点的滤波器可以包括在反馈电路中以呈现第二和第二或更高阶PLL动态。 CPLL允许相干解调极低的FM调制指数，从而输入频率漂移可能大于频率偏差。 它也可以用于相干解调具有组合幅度和相位特性的信号。