公开(公告)号：US07166542B2

公开(公告)日：2007-01-23

申请号：US10707112

申请日：2003-11-21

Applicant: Ming-Hung Lo ,  Liang-Pin Chou ,  Chun-Ming Wang ,  Li-Fu Chen

Inventor： Ming-Hung Lo ,  Liang-Pin Chou ,  Chun-Ming Wang ,  Li-Fu Chen

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/76834 ,  H01L21/76832

Abstract: A method of fabricating a passivation layer is provided. A substrate with a plurality of device structures and at least an interconnect thereon is provided. A patterned metallic layer is formed over the interconnection layer. A plasma-enhanced chemical vapor deposition process is performed to form a first passivation over the metallic layer such that the processing pressure is higher (and/or the processing power is lower) than the pressure (the power) used in prior art. A moisture impermeable second passivation is formed over the first passivation layer. With the first passivation formed in a higher processing pressure (and/or lower processing power), damages to metallic layers or devices due to plasma bombardment is minimized.

Abstract translation: 提供一种制造钝化层的方法。 提供具有多个器件结构并且至少在其上的互连的衬底。 在互连层上形成图案化的金属层。 执行等离子体增强化学气相沉积工艺以在金属层上形成第一钝化，使得处理压力比现有技术中使用的压力（功率）更高（和/或处理能力较低）。 在第一钝化层上形成不透水的第二钝化。 由于在较高的处理压力（和/或较低的处理能力）下形成的第一钝化，由于等离子体轰击而对金属层或器件造成的损害最小化。

公开(公告)号：US06818547B2

公开(公告)日：2004-11-16

申请号：US10229734

申请日：2002-08-27

Applicant: Meng-Hung Chen ,  Yu-Sheng Shu ,  Ming Hung Lo ,  Chung-Yuan Lee

Inventor： Meng-Hung Chen ,  Yu-Sheng Shu ,  Ming Hung Lo ,  Chung-Yuan Lee

IPC: H01L214763

CPC classification number: H01L21/76844 ,  H01L21/76808 ,  H01L21/76877

Abstract: A dual damascene process for producing interconnects. A dielectric layer is formed over the surface of a semiconductor substrate which comprises conductive layers or MOS devices. The dielectric layer is patterned to form trench openings and a metal layer is deposited over the dielectric layer to fill the plurality of trenches. A photoresist layer is formed over the metal layer and defined to form via hole patterns above the trenches. The metal layer and the dielectric layer are etched with the patterned photoresist layer as a mask to form a plurality of via holes exposing the underlying conductive layer or MOS devices and a dual damascene opening is formed.

Abstract translation: 用于生产互连的双镶嵌工艺。 在包括导电层或MOS器件的半导体衬底的表面上形成电介质层。 图案化电介质层以形成沟槽开口，并且在电介质层上沉积金属层以填充多个沟槽。 光致抗蚀剂层形成在金属层之上，并被限定为在沟槽上形成通孔图案。 用图案化的光致抗蚀剂层作为掩模蚀刻金属层和电介质层，以形成暴露下面的导电层或MOS器件的多个通孔，并形成双镶嵌开口。

公开(公告)号：US20050074964A1

公开(公告)日：2005-04-07

申请号：US10707112

申请日：2003-11-21

Applicant: Ming-Hung Lo ,  Liang-Pin Chou ,  Chun-Ming Wang ,  Li-Fu Chen

Inventor： Ming-Hung Lo ,  Liang-Pin Chou ,  Chun-Ming Wang ,  Li-Fu Chen

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76834 ,  H01L21/76832

Abstract: A method of fabricating a passivation layer is provided. A substrate with a plurality of device structures and at least an interconnect thereon is provided. A patterned metallic layer is formed over the interconnection layer. A plasma-enhanced chemical vapor deposition process is performed to form a first passivation over the metallic layer such that the processing pressure is higher (and/or the processing power is lower) than the pressure (the power) used in prior art. A moisture impermeable second passivation is formed over the first passivation layer. With the first passivation formed in a higher processing pressure (and/or lower processing power), damages to metallic layers or devices due to plasma bombardment is minimized.

Abstract translation: 提供一种制造钝化层的方法。 提供具有多个器件结构并且至少在其上的互连的衬底。 在互连层上形成图案化的金属层。 执行等离子体增强化学气相沉积工艺以在金属层上形成第一钝化，使得处理压力比现有技术中使用的压力（功率）更高（和/或处理能力较低）。 在第一钝化层上形成不透水的第二钝化。 由于在较高的处理压力（和/或较低的处理能力）下形成的第一钝化，由于等离子体轰击而对金属层或器件造成的损害最小化。

公开(公告)号：US5795837A

公开(公告)日：1998-08-18

申请号：US697697

申请日：1996-08-28

Applicant: Wen-Cheng J. Wei ,  Ming-Hung Lo ,  Feng-Huei Cheng

Inventor： Wen-Cheng J. Wei ,  Ming-Hung Lo ,  Feng-Huei Cheng

IPC: C04B35/117 ,  C04B35/565 ,  C04B35/575 ,  C04B35/58

CPC classification number: C04B35/575 ,  C04B35/117 ,  C04B35/565

Abstract: The present invention provides a process for preparing a molybdenum, molybdenum silicide or molybdenum carbide/ceramic admixture, comprising dissolving molybdenum trioxide powder with an alkaline solvent to obtain an aqueous solution of molybdate; incorporating ceramic powder with or without silicon and/or carbon powder into the aqueous solution of molybdate to obtain a slurry; and subjecting the slurry to spray drying and reduction to obtain the admixture. The obtained admixture can be formed and sintered into a nanometer-sized and uniformly dispersed molybdenum, molybdenum silicide or molybdenum carbide/ceramic sintered composites.

Abstract translation: 本发明提供了制备钼，硅化钼或碳化钼/陶瓷混合物的方法，其中包括用三氧化硫粉末与碱性溶剂一起溶解以得到钼酸盐水溶液; 将具有或不具有硅和/或碳粉末的陶瓷粉末掺入钼酸盐水溶液中以获得浆料; 并对浆料进行喷雾干燥和还原以获得混合物。 所得混合物可以形成并烧结成纳米尺寸均匀分散的钼，硅化钼或碳化钼/陶瓷烧结复合材料。