公开(公告)号：US08854290B2

公开(公告)日：2014-10-07

申请号：US13150777

申请日：2011-06-01

申请人： Yu-An Liu ,  Liang-Hua Yeh

发明人： Yu-An Liu ,  Liang-Hua Yeh

IPC分类号： G09G3/36 ,  G06F13/14

CPC分类号： G09G3/3696 ,  G06F13/14 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2310/0289 ,  G09G2310/08 ,  G09G2320/0247 ,  G09G2340/0435

摘要： A timing controller for a liquid crystal panel and a timing control method thereof are provided. The timing controller includes a timing control unit for analyzing an input signal to generate a system state transition voltage (STV) signal and a base STV signal, and the timing control unit outputs a base trigger signal and a switch trigger signal having asynchronous frame rates to a select unit at the same time. A compare unit determines whether frequencies of the two state signals are same, so that the select unit determines to forward the base trigger signal or the switch trigger signal to a level shift circuit. Finally, a signal-time control unit controls an output time of the base trigger signal, and controls an output time of the switch trigger signal, so that a liquid crystal unit connected to each gate line has an equal charge time.

摘要翻译： 提供了一种用于液晶面板的时序控制器及其定时控制方法。 定时控制器包括用于分析输入信号以产生系统状态转变电压（STV）信号和基本STV信号的定时控制单元，并且定时控制单元输出具有异步帧速率的基本触发信号和开关触发信号， 同时选择单位。 比较单元确定两个状态信号的频率是否相同，使得选择单元确定将基本触发信号或开关触发信号转发到电平移位电路。 最后，信号时间控制单元控制基本触发信号的输出时间，并控制开关触发信号的输出时间，使得连接到每个栅极线的液晶单元具有相等的充电时间。

公开(公告)号：US08305330B2

公开(公告)日：2012-11-06

申请号：US12582716

申请日：2009-10-21

申请人： Yu-Chieh Fang ,  Liang-Hua Yeh

发明人： Yu-Chieh Fang ,  Liang-Hua Yeh

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G2320/0257

摘要： A gate driving circuit of a display panel including a plurality of shift register sets coupled in series is provided. Every shift register set includes a shift register unit and a transistor coupled therewith. The shift register units receive a gate timing signal and an inverted gate timing signal, and one of a first level shift register unit and a last level shift register unit further receives a threshold driving signal. The shift register units respectively output a plurality of gate driving signals sequentially according to the threshold driving signal, the gate timing signal and the inverted gate timing signal. A gate and a first source/drain of each transistor are coupled to receive a gate controlling signal, and a second source/drain of each transistor is coupled to the corresponding shift register unit to output one of the gate driving signals.

摘要翻译： 提供了包括串联耦合的多个移位寄存器组的显示面板的栅极驱动电路。 每个移位寄存器组包括移位寄存器单元和与其耦合的晶体管。 移位寄存器单元接收门定时信号和反相门定时信号，并且第一电平移位寄存器单元和最后电平移位寄存器单元中的一个进一步接收阈值驱动信号。 移位寄存器单元根据阈值驱动信号，门定时信号和反相门定时信号分别输出多个栅极驱动信号。 每个晶体管的栅极和第一源极/漏极被耦合以接收栅极控制信号，并且每个晶体管的第二源极/漏极耦合到相应的移位寄存器单元以输出栅极驱动信号之一。

公开(公告)号：US20080055226A1

公开(公告)日：2008-03-06

申请号：US11468306

申请日：2006-08-30

申请人： Jiao-Lin Huang ,  Liang-Hua Yeh ,  Ho-Ming Su

发明人： Jiao-Lin Huang ,  Liang-Hua Yeh ,  Ho-Ming Su

IPC分类号： G09G3/36

CPC分类号： G09G3/3685 ,  G09G3/3614 ,  G09G2310/0254 ,  G09G2310/027

摘要： A DAC and a source driver using the same, and a driving method for a display device are provided. The DAC comprises a positive polarity resistor string and a negative polarity resistor string. The resistance of each resistor of the positive polarity resistor string is determined based on positive polarity driving voltages. The resistance of each resistor of the negative polarity resistor string is determined based on negative polarity driving voltages. So, the positive and negative polarity driving voltages, which are used for driving the display device, are in symmetric.

摘要翻译： 提供了一种使用DAC的DAC和源驱动器以及用于显示装置的驱动方法。 DAC包括正极性电阻串和负极性电阻串。 正极性电阻串的每个电阻的电阻根据正极驱动电压来确定。 负极性电阻串的每个电阻的电阻基于负极性驱动电压来确定。 因此，用于驱动显示装置的正极和负极驱动电压是对称的。

公开(公告)号：US20070273405A1

公开(公告)日：2007-11-29

申请号：US11769721

申请日：2007-06-28

申请人： Liang-Hua Yeh ,  Ho-Ming Su

发明人： Liang-Hua Yeh ,  Ho-Ming Su

IPC分类号： H03K19/0175

CPC分类号： G09G3/3696 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2310/027

摘要： The present invention provides a voltage divider circuit capable of reducing a number of external devices and lowering the cost and power consumption. The present invention includes a plurality of resistors connected in series, a plurality of buffers and at least one source driver IC. In addition, a first terminal of the first resistor is electrically connected to a DC voltage and the first terminal of each of the remaining resistors is electrically connected to the second terminal of the previous resistor. The second terminal of the last resistor is grounded. The buffers and the resistors are correspondingly electrically connected, wherein the first terminals of the resistors are electrically connected to their corresponding input terminals of buffers. Moreover, the output terminals of the buffers are electrically connected to source driver ICs, wherein the buffers are one of the built-in buffers in each source driver IC.

摘要翻译： 本发明提供一种能够减少多个外部设备并降低成本和功耗的分压电路。 本发明包括串联连接的多个电阻器，多个缓冲器和至少一个源极驱动器IC。 此外，第一电阻器的第一端子电连接到DC电压，并且每个剩余电阻器的第一端子电连接到先前电阻器的第二端子。 最后一个电阻的第二个端子接地。 缓冲器和电阻器相应地电连接，其中电阻器的第一端子电连接到它们对应的缓冲器的输入端子。 此外，缓冲器的输出端子电连接到源极驱动器IC，其中缓冲器是每个源极驱动器IC中的内置缓冲器之一。

公开(公告)号：US07265584B2

公开(公告)日：2007-09-04

申请号：US11163854

申请日：2005-11-01

申请人： Liang-Hua Yeh ,  Ho-Ming Su

发明人： Liang-Hua Yeh ,  Ho-Ming Su

IPC分类号： H03K19/0175

CPC分类号： G09G3/3696 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2310/027

摘要： The present invention provides a voltage divider circuit capable of reducing a number of external devices and lowering the cost and power consumption. The present invention includes a plurality of resistors connected in series, a plurality of buffers and at least one source driver IC. In addition, a first terminal of the first resistor is electrically connected to a DC voltage and the first terminal of each of the remaining resistors is electrically connected to the second terminal of the previous resistor. The second terminal of the last resistor is grounded. The buffers and the resistors are correspondingly electrically connected, wherein the first terminals of the resistors are electrically connected to their corresponding input terminals of buffers. Moreover, the output terminals of the buffers are electrically connected to source driver ICs, wherein the buffers are one of the built-in buffers in each source driver IC.

摘要翻译： 本发明提供一种能够减少多个外部设备并降低成本和功耗的分压电路。 本发明包括串联连接的多个电阻器，多个缓冲器和至少一个源极驱动器IC。 此外，第一电阻器的第一端子电连接到DC电压，并且每个剩余电阻器的第一端子电连接到先前电阻器的第二端子。 最后一个电阻的第二个端子接地。 缓冲器和电阻器相应地电连接，其中电阻器的第一端子电连接到它们对应的缓冲器的输入端子。 此外，缓冲器的输出端子电连接到源极驱动器IC，其中缓冲器是每个源极驱动器IC中的内置缓冲器之一。

公开(公告)号：US20120147018A1

公开(公告)日：2012-06-14

申请号：US13150777

申请日：2011-06-01

申请人： Yu-An LIU ,  Liang-Hua Yeh

发明人： Yu-An LIU ,  Liang-Hua Yeh

IPC分类号： G06F13/14

CPC分类号： G09G3/3696 ,  G06F13/14 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2310/0289 ,  G09G2310/08 ,  G09G2320/0247 ,  G09G2340/0435

摘要： A timing controller for a liquid crystal panel and a timing control method thereof are provided. The timing controller includes a timing control unit for analyzing an input signal to generate a system state transition voltage (STV) signal and a base STV signal, and the timing control unit outputs a base trigger signal and a switch trigger signal having asynchronous frame rates to a select unit at the same time. A compare unit determines whether frequencies of the two state signals are same, so that the select unit determines to forward the base trigger signal or the switch trigger signal to a level shift circuit. Finally, a signal-time control unit controls an output time of the base trigger signal, and controls an output time of the switch trigger signal, so that a liquid crystal unit connected to each gate line has an equal charge time.

摘要翻译： 提供了一种用于液晶面板的时序控制器及其定时控制方法。 定时控制器包括用于分析输入信号以产生系统状态转变电压（STV）信号和基本STV信号的定时控制单元，并且定时控制单元输出具有异步帧速率的基本触发信号和开关触发信号， 同时选择单位。 比较单元确定两个状态信号的频率是否相同，使得选择单元确定将基本触发信号或开关触发信号转发到电平移位电路。 最后，信号时间控制单元控制基本触发信号的输出时间，并控制开关触发信号的输出时间，使得连接到每个栅极线的液晶单元具有相等的充电时间。

公开(公告)号：US20070096967A1

公开(公告)日：2007-05-03

申请号：US11163854

申请日：2005-11-01

申请人： Liang-Hua Yeh ,  Ho-Ming Su

发明人： Liang-Hua Yeh ,  Ho-Ming Su

IPC分类号： H03M1/78

CPC分类号： G09G3/3696 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2310/027

摘要： The present invention provides a voltage divider circuit capable of reducing a number of external devices and lowering the cost and power consumption. The present invention includes a plurality of resistors connected in series, a plurality of buffers and at least one source driver IC. In addition, a first terminal of the first resistor is electrically connected to a DC voltage and the first terminal of each of the remaining resistors is electrically connected to the second terminal of the previous resistor. The second terminal of the last resistor is grounded. The buffers and the resistors are correspondingly electrically connected, wherein the first terminals of the resistors are electrically connected to their corresponding input terminals of buffers. Moreover, the output terminals of the buffers are electrically connected to source driver ICs, wherein the buffers are one of the built-in buffers in each source driver IC.

公开(公告)号：US20130147755A1

公开(公告)日：2013-06-13

申请号：US13396607

申请日：2012-02-15

申请人： Chia-Hsien Lin ,  Liang-Hua Yeh

发明人： Chia-Hsien Lin ,  Liang-Hua Yeh

IPC分类号： G06F3/044 ,  G09G3/36 ,  G06F3/041

CPC分类号： G06F3/0416 ,  G06F3/0418 ,  G06F3/044

摘要： A noise cancellation circuit includes at least one antenna, a multiplexer, and a readout circuit. The at least one antenna is used for coupling noise of a touch panel and noise of a liquid crystal panel coupled to the touch panel. The multiplexer is used for receiving first X axis sensing signals and first Y axis sensing signals of the touch panel. The readout circuit is used for utilizing the noise of the touch panel and the noise of the liquid crystal panel to cancel noise of the touch panel and noise of the liquid crystal panel in the first X axis sensing signals and the first Y axis sensing signals, and to generate and output second X axis sensing signals and second Y axis sensing signals not including the noise of the touch panel and the noise of the liquid crystal panel.

摘要翻译： 噪声消除电路包括至少一个天线，多路复用器和读出电路。 所述至少一个天线用于耦合触摸面板的噪声和耦合到触摸面板的液晶面板的噪声。 多路复用器用于接收触摸面板的第一X轴感测信号和第一Y轴感测信号。 读出电路用于利用触摸面板的噪声和液晶面板的噪声来消除触摸面板的噪声和液晶面板在第一X轴感测信号和第一Y轴感测信号中的噪声， 并且产生并输出不包括触摸面板的噪声和液晶面板的噪声的第二X轴感测信号和第二Y轴感测信号。

公开(公告)号：US20120105493A1

公开(公告)日：2012-05-03

申请号：US13029750

申请日：2011-02-17

申请人： Chien-Lin YEH ,  Liang-Hua Yeh

发明人： Chien-Lin YEH ,  Liang-Hua Yeh

IPC分类号： G09G5/10

CPC分类号： G09G3/3677 ,  G09G2320/0209 ,  G09G2320/0223 ,  G09G2320/0247 ,  G09G2330/06

摘要： A shading signal generating circuit includes an output port, a first switch, a second switch, a third switch, a first control unit, a second control unit, and a resistor. The output port is electrically connected to the first switch, the second switch, and the third switch. The first switch is electrically connected to a first voltage source and switched on according to a clock signal. The second switch is electrically connected to a second voltage source. The first control unit converts the clock signal to an inverse clock signal, thereby outputting a switch signal for switching on the second switch. The resistor is connected between a third voltage source and the third switch in series. The third switch controls the electric connection between the output port and the third voltage source. The second control unit switches on the third switch according to the inverse clock signal and the switch signal.

摘要翻译： 遮蔽信号发生电路包括输出端口，第一开关，第二开关，第三开关，第一控制单元，第二控制单元和电阻器。 输出端口电连接到第一开关，第二开关和第三开关。 第一开关电连接到第一电压源，并根据时钟信号接通。 第二开关电连接到第二电压源。 第一控制单元将时钟信号转换为反时钟信号，由此输出用于接通第二开关的开关信号。 电阻器连接在第三电压源和第三开关之间。 第三开关控制输出端口和第三电压源之间的电气连接。 第二控制单元根据逆时钟信号和开关信号来接通第三开关。

公开(公告)号：US20110025658A1

公开(公告)日：2011-02-03

申请号：US12582716

申请日：2009-10-21

申请人： Yu-Chieh Fang ,  Liang-Hua Yeh

发明人： Yu-Chieh Fang ,  Liang-Hua Yeh

IPC分类号： G06F3/038

CPC分类号： G09G3/3677 ,  G09G2320/0257

摘要： A gate driving circuit of a display panel including a plurality of shift register sets coupled in series is provided. Every shift register set includes a shift register unit and a transistor coupled therewith. The shift register units receive a gate timing signal and an inverted gate timing signal, and one of a first level shift register unit and a last level shift register unit further receives a threshold driving signal. The shift register units respectively output a plurality of gate driving signals sequentially according to the threshold driving signal, the gate timing signal and the inverted gate timing signal. A gate and a first source/drain of each transistor are coupled to receive a gate controlling signal, and a second source/drain of each transistor is coupled to the corresponding shift register unit to output one of the gate driving signals.

摘要翻译： 提供了包括串联耦合的多个移位寄存器组的显示面板的栅极驱动电路。 每个移位寄存器组包括移位寄存器单元和与其耦合的晶体管。 移位寄存器单元接收门定时信号和反相门定时信号，并且第一电平移位寄存器单元和最后电平移位寄存器单元中的一个进一步接收阈值驱动信号。 移位寄存器单元根据阈值驱动信号，门定时信号和反相门定时信号分别输出多个栅极驱动信号。 每个晶体管的栅极和第一源极/漏极被耦合以接收栅极控制信号，并且每个晶体管的第二源极/漏极耦合到相应的移位寄存器单元以输出栅极驱动信号之一。