摘要:
A method for eliminating the Fourier analysis noise floor generated by a circuit simulator is disclosed. This is accomplished by making the simulator behavior during each Fourier analysis sample interval (704) algorithmically identical to that employed during every other sample interval. Thus between each Fourier analysis sample point (703), the step size, number of iterations, integration method, etc., are allowed to vary as needed with the proviso that each sample interval uses exactly the same sequence of time steps, and that each member of that sequence is algorithmically identical to the corresponding members in the sequences used on every other Fourier sample interval. In other words, the first time step in the first interval must be algorithmically identical to the first time step in every other interval. The same is true for the second step, the third step, and so on until the last step.
摘要:
An extension to a simulator (801) that allows the user to specify real numbers, voltages, and currents (808) on ports of an electrical net is presented. The computer using the analog wire functionality routines (805), the routines for determining nets (804), the net manager (803), and the pin manager (802) resolves unspecified values on said electrical nets. The user may specify at least one value on said port and may specify whether said port is driven. The extension includes additional math functions (1901).
摘要:
A design specifications-driven platform (100) for analog, mixed-signal and radio frequency verification with one embodiment comprising a client (160) and server (150) is presented. The server comprises an analog verification database (110), a code and document generator (1020), a design to specifications consistency checker (103), a symbol generator (104), a coverage analyzer (105), a server interface (106), a web server (111), and an analog verification server application (101). The client comprises a web browser (130), generated datasheets and reports (120), generated models, regression tests, netlists, connect modules, and symbols (121), generated simulation scripts (122), a client interface (124), design data (131), simulators (132), and a design data extractor (123).