公开(公告)号：US06756624B2

公开(公告)日：2004-06-29

申请号：US10409010

申请日：2003-04-07

Applicant: Kevin S. Petrarca ,  Donald Canaperi ,  Mahadevaiyer Krishnan ,  Kenneth Jay Stein ,  Richard P. Volant

Inventor： Kevin S. Petrarca ,  Donald Canaperi ,  Mahadevaiyer Krishnan ,  Kenneth Jay Stein ,  Richard P. Volant

IPC: H01L27108

CPC classification number: H01L21/76849 ,  H01L21/76834 ,  H01L21/7684 ,  H01L28/60

Abstract: A method is described for fabricating an encapsulated metal structure in a feature formed in a substrate. The sidewalls and bottom of the feature are covered by a barrier layer and the feature is filled with metal, preferably by electroplating. A recess is formed in the metal, and an additional barrier layer is deposited, covering the top surface of the metal and contacting the first barrier layer. The additional barrier layer is planarized, preferably by chemical-mechanical polishing. The method may be used in fabricating a MIM capacitor, with the encapsulated metal structure serving as the lower plate of the capacitor. A second substrate layer is deposited on the top surface of the substrate, with an opening overlying the encapsulated metal structure. A dielectric layer is deposited in the opening, covering the encapsulated metal structure at the bottom thereof. An additional layer, serving as the upper plate of the capacitor, is deposited to cover the dielectric layer and to fill the opening. The dielectric layer and the additional layer are planarized, preferably by CMP.

Abstract translation: 描述了一种在衬底中形成的特征中制造封装金属结构的方法。 特征的侧壁和底部被阻挡层覆盖，并且该特征被金属填充，优选地通过电镀。 在金属中形成凹部，并且沉积附加的阻挡层，覆盖金属的顶表面并与第一阻挡层接触。 优选通过化学机械抛光将附加阻挡层平坦化。 该方法可用于制造MIM电容器，其中封装的金属结构用作电容器的下板。 第二衬底层沉积在衬底的顶表面上，具有覆盖封装的金属结构的开口。 介电层沉积在开口中，覆盖其底部的封装金属结构。 作为电容器的上板的附加层被沉积以覆盖电介质层并填充开口。 介电层和附加层优选通过CMP平坦化。

公开(公告)号：US06597068B2

公开(公告)日：2003-07-22

申请号：US10034862

申请日：2001-12-28

Applicant: Kevin S. Petrarca ,  Donald Canaperi ,  Mahadevaiyer Krishnan ,  Kenneth Jay Stein ,  Richard P. Volant

Inventor： Kevin S. Petrarca ,  Donald Canaperi ,  Mahadevaiyer Krishnan ,  Kenneth Jay Stein ,  Richard P. Volant

IPC: H01L2348

CPC classification number: H01L21/76849 ,  H01L21/76834 ,  H01L21/7684 ,  H01L28/60

Abstract: A method is described for fabricating an encapsulated metal structure in a feature formed in a substrate. The sidewalls and bottom of the feature are covered by a barrier layer and the feature is filled with metal, preferably by electroplating. A recess is formed in the metal, and an additional barrier layer is deposited, covering the top surface of the metal and contacting the first barrier layer. The additional barrier layer is planarized, preferably by chemical-mechanical polishing. The method may be used in fabricating a MIM capacitor, with the encapsulated metal structure serving as the lower plate of the capacitor. A second substrate layer is deposited on the top surface of the substrate, with an opening overlying the encapsulated metal structure. A dielectric layer is deposited in the opening, covering the encapsulated metal structure at the bottom thereof. An additional layer, serving as the upper plate of the capacitor, is deposited to cover the dielectric layer and to fill the opening. The dielectric layer and the additional layer are planarized, preferably by CMP.

公开(公告)号：US06368953B1

公开(公告)日：2002-04-09

申请号：US09567466

申请日：2000-05-09

Applicant: Kevin S. Petrarca ,  Donald Canaperi ,  Mahadevaiyer Krishnan ,  Kenneth Jay Stein ,  Richard P. Volant

Inventor： Kevin S. Petrarca ,  Donald Canaperi ,  Mahadevaiyer Krishnan ,  Kenneth Jay Stein ,  Richard P. Volant

IPC: H01L214763

CPC classification number: H01L21/76849 ,  H01L21/76834 ,  H01L21/7684 ,  H01L28/60

Abstract: A method is described for fabricating an encapsulated metal structure in a feature formed in a substrate. The sidewalls and bottom of the feature are covered by a barrier layer and the feature is filled with metal, preferably by electroplating. A recess is formed in the metal, and an additional barrier layer is deposited, covering the top surface of the metal and contacting the first barrier layer. The additional barrier layer is planarized, preferably by chemical-mechanical polishing. The method may be used in fabricating a MIM capacitor, with the encapsulated metal structure serving as the lower plate of the capacitor. A second substrate layer is deposited on the top surface of the substrate, with an opening overlying the encapsulated metal structure. A dielectric layer is deposited in the opening, covering the encapsulated metal structure at the bottom thereof. An additional layer, serving as the upper plate of the capacitor, is deposited to cover the dielectric layer and to fill the opening. The dielectric layer and the additional layer are planarized, preferably by CMP.

Abstract translation: 描述了一种在衬底中形成的特征中制造封装金属结构的方法。 特征的侧壁和底部被阻挡层覆盖，并且该特征被金属填充，优选地通过电镀。 在金属中形成凹部，并且沉积附加的阻挡层，覆盖金属的顶表面并与第一阻挡层接触。 优选通过化学机械抛光将附加阻挡层平坦化。 该方法可用于制造MIM电容器，其中封装的金属结构用作电容器的下板。 第二衬底层沉积在衬底的顶表面上，具有覆盖封装的金属结构的开口。 介电层沉积在开口中，覆盖其底部的封装金属结构。 作为电容器的上板的附加层被沉积以覆盖电介质层并填充开口。 介电层和附加层优选通过CMP平坦化。

公开(公告)号：US07898063B2

公开(公告)日：2011-03-01

申请号：US12032642

申请日：2008-02-16

Applicant: Peter James Lindgren ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper ,  Kenneth Jay Stein

Inventor： Peter James Lindgren ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper ,  Kenneth Jay Stein

IPC: H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer.

Abstract translation: 贯通基板通孔包括在通孔基板孔周边的环形导体层和被环形导体层围绕的塞子层。 一种用于制造贯通衬底通孔的方法，包括在衬底内形成盲孔，并在盲孔内依次形成并随后在盲孔内进行平面化，该保形导体层不填充填充孔的孔和塞层。 然后可以将衬底的背面平坦化以至少露出平坦化的共形导体层。

公开(公告)号：US20110129996A1

公开(公告)日：2011-06-02

申请号：US13025678

申请日：2011-02-11

Applicant: Peter James Lindgren ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper ,  Kenneth Jay Stein

Inventor： Peter James Lindgren ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper ,  Kenneth Jay Stein

IPC: H01L21/28

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer.

Abstract translation: 贯通基板通孔包括在通孔基板孔周边的环形导体层和被环形导体层围绕的塞子层。 一种用于制造贯通衬底通孔的方法，包括在衬底内形成盲孔，并在盲孔内依次形成并随后在盲孔内进行平面化，该保形导体层不填充填充孔的孔和塞层。 然后可以将衬底的背面平坦化以至少露出平坦化的共形导体层。

公开(公告)号：US20090206488A1

公开(公告)日：2009-08-20

申请号：US12032642

申请日：2008-02-16

Applicant: Peter James Lindgren ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper ,  Kenneth Jay Stein

Inventor： Peter James Lindgren ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper ,  Kenneth Jay Stein

IPC: H01L21/768 ,  H01L23/538

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer.

Abstract translation: 贯通基板通孔包括在通孔基板孔周边的环形导体层和被环形导体层围绕的塞子层。 一种用于制造贯通衬底通孔的方法，包括在衬底内形成盲孔，并在盲孔内依次形成并随后在盲孔内进行平面化，该保形导体层不填充填充孔的孔和塞层。 然后可以将衬底的背面平坦化以至少露出平坦化的共形导体层。

公开(公告)号：US06825075B2

公开(公告)日：2004-11-30

申请号：US10757214

申请日：2004-01-14

Applicant: Kevin S. Petrarca ,  Donald Canaperi ,  Mahadevaiyer Krishnan ,  Kenneth Jay Stein ,  Richard P. Volant

Inventor： Kevin S. Petrarca ,  Donald Canaperi ,  Mahadevaiyer Krishnan ,  Kenneth Jay Stein ,  Richard P. Volant

IPC: H01L218242

CPC classification number: H01L21/76849 ,  H01L21/76834 ,  H01L21/7684 ,  H01L28/60

Abstract: A method is described for fabricating an encapsulated metal structure in a feature formed in a substrate. The sidewalls and bottom of the feature are covered by a barrier layer and the feature is filled with metal, preferably by electroplating. A recess is formed in the metal, and an additional barrier layer is deposited, covering the top surface of the metal and contacting the first barrier layer. The additional barrier layer is planarized, preferably by chemical-mechanical polishing. The method may be used in fabricating a MIM capacitor, with the encapsulated metal structure serving as the lower plate of the capacitor. A second substrate layer is deposited on the top surface of the substrate, with an opening overlying the encapsulated metal structure. A dielectric layer is deposited in the opening, covering the encapsulated metal structure at the bottom thereof. An additional layer, serving as the upper plate of the capacitor, is deposited to cover the dielectric layer and to fill the opening. The dielectric layer and the additional layer are planarized, preferably by CMP.

Abstract translation: 描述了一种在衬底中形成的特征中制造封装金属结构的方法。 特征的侧壁和底部被阻挡层覆盖，并且该特征被金属填充，优选地通过电镀。 在金属中形成凹部，并且沉积附加的阻挡层，覆盖金属的顶表面并与第一阻挡层接触。 优选通过化学机械抛光将附加阻挡层平坦化。 该方法可用于制造MIM电容器，其中封装的金属结构用作电容器的下板。 第二衬底层沉积在衬底的顶表面上，具有覆盖封装的金属结构的开口。 介电层沉积在开口中，覆盖其底部的封装金属结构。 作为电容器的上板的附加层被沉积以覆盖电介质层并填充开口。 介电层和附加层优选通过CMP平坦化。

公开(公告)号：US5926359A

公开(公告)日：1999-07-20

申请号：US626310

申请日：1996-04-01

Applicant: Nancy Anne Greco ,  David Louis Harame ,  Gary Robert Hueckel ,  Joseph Thomas Kocis ,  Dominique Nguyen Ngoc ,  Kenneth Jay Stein

Inventor： Nancy Anne Greco ,  David Louis Harame ,  Gary Robert Hueckel ,  Joseph Thomas Kocis ,  Dominique Nguyen Ngoc ,  Kenneth Jay Stein

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01G4/06

CPC classification number: H01L23/5223 ,  H01L28/40 ,  H01L2924/0002

Abstract: An interconnection wiring system incorporating two levels of interconnection wiring separated by a first dielectric, a capacitor formed by a second dielectric, a bottom electrode of the lower interconnection wiring or a via and a top electrode of the upper interconnection wiring or a separate metal layer. The invention overcomes the problem of leakage current and of substrate stray capacitance by positioning the capacitor between two levels of interconnection wiring.

公开(公告)号：US08159040B2

公开(公告)日：2012-04-17

申请号：US12119526

申请日：2008-05-13

Applicant: Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Ephrem G. Gebreselasie ,  Zhong-Xiang He ,  Herbert Lei Ho ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Robert Mark Rassel ,  John Matthew Safran ,  Kenneth Jay Stein ,  Norman Whitelaw Robson ,  Ping-Chuan Wang ,  Hongwen Yan

Inventor： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Ephrem G. Gebreselasie ,  Zhong-Xiang He ,  Herbert Lei Ho ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Robert Mark Rassel ,  John Matthew Safran ,  Kenneth Jay Stein ,  Norman Whitelaw Robson ,  Ping-Chuan Wang ,  Hongwen Yan

IPC: H01L29/00

CPC classification number: H01L27/0629 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.

Abstract translation: 半导体结构和半导体结构的制造方法提供一种场效应器件，其位于和形成在半导体衬底的有源区上，并且至少一个熔丝结构，抗熔丝结构和电阻结构中的至少一个至少位于并形成 部分地同时地在与半导体衬底内的有源区域横向分离的隔离区域上。 场效应器件包括包括高介电常数介电材料的栅极电介质和包括金属材料的栅电极。 熔丝结构，反熔丝结构和电阻器结构中的至少一个包括包括与栅极电介质相同的材料的焊盘电介质，以及可选地还包括熔断器，反熔丝或电阻器，其可以包括与所述栅极电介质相同的金属材料 栅电极。

公开(公告)号：US06927440B2

公开(公告)日：2005-08-09

申请号：US10658036

申请日：2003-09-09

Applicant: Nancy Anne Greco ,  David Louis Harame ,  Gary Robert Hueckel ,  Joseph Thomas Kocis ,  Dominique Nguyen Ngoc ,  Kenneth Jay Stein

Inventor： Nancy Anne Greco ,  David Louis Harame ,  Gary Robert Hueckel ,  Joseph Thomas Kocis ,  Dominique Nguyen Ngoc ,  Kenneth Jay Stein

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L27/108 ,  H01L29/41

CPC classification number: H01L23/5223 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnection wiring system incorporating two levels of interconnection wiring separated by a first dielectric, a capacitor formed by a second dielectric, a bottom electrode of the lower interconnection wiring or a via and a top electrode of the upper interconnection wiring or a separate metal layer. The invention overcomes the problem of leakage current and of substrate stray capacitance by positioning the capacitor between two levels of interconnection wiring.