公开(公告)号：US07636007B2

公开(公告)日：2009-12-22

申请号：US10937982

申请日：2004-09-10

申请人： Myles Wakayama ,  Stephen A. Jantzi ,  Kwang Young Kim ,  Yee Ling “Felix” Cheung ,  Ka Wai Tong

发明人： Myles Wakayama ,  Stephen A. Jantzi ,  Kwang Young Kim ,  Yee Ling “Felix” Cheung ,  Ka Wai Tong

IPC分类号： H03K17/00

CPC分类号： H03L7/0996 ,  H03L7/0891 ,  H03L7/183

摘要： A low jitter, high phase resolution phase lock loop incorporating a ring oscillator-type VCO is designed and constructed to operate at a characteristic frequency M times higher than a required output clock frequency. Multi-phase output signals are taken from the VCO and selected through a Gray code MUX, prior to being divided down to the output clock frequency by a divide-by-M frequency divider circuit. Operating the VCO at frequencies in excess of the output clock frequency, allows jitter to be averaged across a timing cycle M and further allows a reduction in the number of output phase taps, by a scale factor M, without reducing the phase resolution or granularity of the output signal.

摘要翻译： 包含环形振荡器型VCO的低抖动，高相位分辨率锁相环被设计和构造成以比要求的输出时钟频率M倍高的特征频率工作。 在通过M分频电路将其分频到输出时钟频率之前，通过格雷码MUX从VCO中取出多相输出信号。 在超过输出时钟频率的频率下操作VCO允许在定时周期M之间平均抖动，并且进一步允许减小比例因子M的输出相位抽头的数量，而不会降低相位分辨率或粒度 输出信号。

公开(公告)号：US06791379B1

公开(公告)日：2004-09-14

申请号：US09456230

申请日：1999-12-07

申请人： Myles Wakayama ,  Stephen A. Jantzi ,  Kwang Young Kim ,  Yee Ling Felix Cheung ,  Ka Wai Tong

发明人： Myles Wakayama ,  Stephen A. Jantzi ,  Kwang Young Kim ,  Yee Ling Felix Cheung ,  Ka Wai Tong

IPC分类号： H03L706

CPC分类号： H03L7/0996 ,  H03L7/0891 ,  H03L7/183

摘要： A low jitter, high phase resolution phase lock loop incorporating a ring oscillator-type VCO is designed and constructed to operate at a characteristic frequency M times higher than a required output clock frequency. Multi-phase output signals are taken from the VCO and selected through a Gray code MUX, prior to being divided down to the output clock frequency by a divide-by-M frequency divider circuit. Operating the VCO at frequencies in excess of the output clock frequency, allows jitter to be averaged across a timing cycle M and further allows a reduction in the number of output phase taps, by a scale factor M, without reducing the phase resolution or granularity of the output signal.

摘要翻译： 包含环形振荡器型VCO的低抖动，高相位分辨率锁相环被设计和构造成以比要求的输出时钟频率M倍高的特征频率工作。 在通过M分频电路将其分频到输出时钟频率之前，通过格雷码MUX从VCO中取出多相输出信号。 在超过输出时钟频率的频率下操作VCO允许在定时周期M之间平均抖动，并且进一步允许减小比例因子M的输出相位抽头的数量，而不会降低相位分辨率或粒度 输出信号。