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    Bank selection signal control circuit for use in semiconductor memory device, and bank selection control method
    1.
    发明授权
    Bank selection signal control circuit for use in semiconductor memory device, and bank selection control method 失效
    用于半导体存储器件的存储体选择信号控制电路，以及存储体选择控制方法

    公开(公告)号：US07289385B2

    公开(公告)日：2007-10-30

    申请号：US11270899

    申请日：2005-11-12

    申请人： Jin-Seok Kwak

    发明人： Jin-Seok Kwak

    IPC分类号： G11C8/00

    CPC分类号： G11C8/12 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C11/4087 ,  G11C11/4093

    摘要： Memory bank selection control circuits and methods are provided which improve the data sensing margin for data sense amplifiers in a multi-bank semiconductor memory structure. In one aspect, a bank selection signal control circuit includes a bank switch control unit that receives memory bank selection signals and outputs corresponding memory bank selection control signals to selectively connect memory banks to a global data input/output line according to a predetermined sequence. For memory bank selected prior to a last selected memory bank in the predetermined sequence, the bank switch control unit outputs memory bank selection control signals that are enabled for a first time period P1, and for the last selected memory bank, the bank switch control unit outputs a memory bank selection control signal that is enabled for a second time period P2, wherein P2 is greater than P1. A switching unit sequentially connects each selected memory bank to the global data input/output line according to the predetermined sequence, and for a predetermined period P1 or P2, in response to the corresponding bank selection control signals.

    摘要翻译： 提供了存储体选择控制电路和方法，其提高了多存储体半导体存储器结构中的数据读出放大器的数据感测余量。 一方面，存储体选择信号控制电路包括存储体开关控制单元，其接收存储体选择信号并输出​​相应的存储体选择控制信号，以根据预定顺序选择性地将存储体连接到全局数据输入/输出线。 对于以预定顺序在最后一个选择的存储体之前选择的存储体，存储体开关控制单元输出第一时间段P 1使能的存储体选择控制信号，并且对于最后选择的存储体，存储体开关控制 单元输出在第二时间段P 2中使能的存储体选择控制信号，其中P 2大于P 1。 开关单元响应于相应的存储体选择控制信号，按照预定顺序依次连接每个所选择的存储体与全局数据输入/输出线，并且对于预定周期P 1或P 2。

    Semiconductor memory device having external data load signal synchronous with data strobe signal and serial-to-parallel data prefetch method thereof
    2.
    发明授权
    Semiconductor memory device having external data load signal synchronous with data strobe signal and serial-to-parallel data prefetch method thereof 失效
    具有与数据选通信号同步的外部数据负载信号及其串并行数据预取方法的半导体存储器件

    公开(公告)号：US07200069B2

    公开(公告)日：2007-04-03

    申请号：US10273512

    申请日：2002-10-18

    申请人： Seong-Jin Jang ,  Jin-Seok Kwak

    发明人： Seong-Jin Jang ,  Jin-Seok Kwak

    IPC分类号： G06F12/00

    CPC分类号： G11C7/1087 ,  G06F13/1689 ,  G11C7/1078 ,  G11C2207/107

    摘要： A semiconductor memory system, a memory control circuit and a semiconductor memory device are disclosed. The system includes a memory control circuit for generating a data strobe signal and a data load signal in synchronization with each other. The memory circuit, which can be an SDRAM memory circuit, receives the data strobe signal and the data load signal and writes data in response to the two synchronous signals. Because the signal are synchronous, parameters introduced by timing variations caused by different signal domains are eliminated. As a result, high-frequency operation of the system is greatly improved.

    摘要翻译： 公开了半导体存储器系统，存储器控制电路和半导体存储器件。 该系统包括用于彼此同步地产生数据选通信号和数据负载信号的存储器控​​制电路。 可以是SDRAM存储器电路的存储电路接收数据选通信号和数据负载信号，并响应于两个同步信号写入数据。 由于信号是同步的，消除了由不同信号域引起的定时变化引入的参数。 结果，系统的高频操作大大提高。

    Circuit and method for controlling on-die signal termination
    3.
    发明授权
    Circuit and method for controlling on-die signal termination 有权
    用于控制片上信号终止的电路和方法

    公开(公告)号：US06762620B2

    公开(公告)日：2004-07-13

    申请号：US10235694

    申请日：2002-09-05

    申请人： Seong-Jin Jang ,  Jin-Seok Kwak

    发明人： Seong-Jin Jang ,  Jin-Seok Kwak

    IPC分类号： H03K1716

    CPC分类号： H04L25/0298 ,  H03K19/0005

    摘要： A system and method allows for multiple modes of termination, including termination by a fixed value that is preprogrammed, and by a variable value that can, for example, be measured and determined by a self-calibration circuit. Multiple termination values can be achieved within a single device. This configuration is especially applicable to devices that have different loadings for address and data signals, for example in a configuration having a common, shared address bus, and multiple, localized data buses.

    摘要翻译： 系统和方法允许多种终止模式，包括通过预编程的固定值的终止，以及可以例如由自校准电路测量和确定的可变值。 可以在单个设备内实现多个终止值。 该配置特别适用于具有地址和数据信号的不同负载的设备，例如在具有公共共享地址总线和多个本地化数据总线的配置中。

    Synchronous memory devices with synchronized latency control circuits and methods of operating same
    4.
    发明授权
    Synchronous memory devices with synchronized latency control circuits and methods of operating same 失效

    公开(公告)号：US06643215B2

    公开(公告)日：2003-11-04

    申请号：US10025703

    申请日：2001-12-19

    申请人： Jin-seok Kwak

    发明人： Jin-seok Kwak

    IPC分类号： G11C800

    CPC分类号： G11C7/1045 ,  G11C7/1072

    摘要： A first clock signal is processed to produce a second clock signal that lags the first clock signal by a first predetermined time and a third clock signal that leads the first clock signal by a second predetermined time. A synchronous read status signal generator circuit receives a read initiation signal indicative of initiation of a read operation and a read termination signal indicative of termination of the read operation. The synchronous read status signal generator circuit produces a transition in a read status signal in response to assertion of either of the read initiation signal or the read termination signal, and latches the read status signal responsive to the second clock signal to generate a synchronized read status signal. A latency signal generator circuit receives the synchronized read status signal and generates a latency control signal therefrom responsive to the third clock signal. Output of data from the memory device is controlled responsive to the latency control signal.

    Semiconductor memory device and redundancy method thereof
    5.
    发明授权
    Semiconductor memory device and redundancy method thereof 失效
    半导体存储器件及其冗余方法

    公开(公告)号：US06590814B1

    公开(公告)日：2003-07-08

    申请号：US09717889

    申请日：2000-11-20

    申请人： Jin Seok Kwak

    发明人： Jin Seok Kwak

    IPC分类号： G11C700

    CPC分类号： G11C29/785 ,  G11C29/848

    摘要： In a semiconductor memory device that includes memory cell array banks, memory cell array blocks in each memory cell array bank, partial blocks in each memory cell array block, data input/output line pairs connected to the partial blocks, and a predetermined number of redundant partial blocks connected to a predetermined number of redundant data input/output line pairs, the semiconductor memory device further includes an address setting circuit to set a redundant control signal and a defect address of each of the memory cell array blocks, decoder and shifting control signal generating circuits to generate shifting control signals to control shifting of the data input/output line pairs and the predetermined number of redundant data input/output line pairs by decoding the redundant control signal and the defective address, and switching circuits for routing data through data input/output line pairs adjacent to a corresponding data input/output line pairs in response to each of the shifting control signals. Therefore, the semiconductor memory device can generate the shifting control signals dynamically to column cycle and can construct a redundancy circuit with a small number of fuses.

    摘要翻译： 在包括存储单元阵列组的半导体存储器件中，每个存储单元阵列组中的存储单元阵列块，每个存储单元阵列块中的部分块，连接到该部分块的数据输入/输出线对以及预定数量的冗余 连接到预定数量的冗余数据输入/输出线对的部分块，所述半导体存储器件还包括地址设置电路，用于设置每个存储单元阵列块的冗余控制信号和缺陷地址，解码器和移位控制信号 生成电路以通过解码冗余控制信号和缺陷地址来产生移位控制信号以控制数据输入/输出线对和预定数量的冗余数据输入/输出线对的移位，以及用于通过数据输入路由数据的切换电路 /输出线对对应于相应的数据输入/输出线对，以响应每个移位 ng控制信号。 因此，半导体存储器件可以动态地产生移位控制信号到列周期，并且可以构造具有少量熔丝的冗余电路。

    Merged memory and logic (MML) integrated circuit devices including buffer memory and methods of detecting errors therein
    6.
    发明授权
    Merged memory and logic (MML) integrated circuit devices including buffer memory and methods of detecting errors therein 有权
    合并的存储器和逻辑（MML）集成电路器件包括缓冲存储器和检测错误的方法

    公开(公告)号：US06175524B1

    公开(公告)日：2001-01-16

    申请号：US09351728

    申请日：1999-07-12

    申请人： Jin-seok Kwak

    发明人： Jin-seok Kwak

    IPC分类号： G11C700

    CPC分类号： G11C29/38 ,  G01R31/318572 ,  G11C7/1006 ,  G11C2207/104

    摘要： An MML integrated circuit device includes a memory block, a logic circuit and a buffer memory, and a selection circuit that is coupled between the logic circuit and the buffer memory. The first selection portion is responsive to external data and to the logic circuit, to transmit external data or data from the logic circuit to the memory block via the buffer memory. Thus, MML integrated circuit devices can use the buffer memory to access the memory block during a normal operational mode and during a test mode. MML integrated circuit devices also preferably include a data expansion portion that is coupled between the external data and the selection portion, to replicate the external data a predetermined number of times and to transmit the replicated external data to the selection portion. Errors may be detected in an MML integrated circuit device that includes a memory block, a logic circuit and a buffer memory, by storing external data from external of the MML integrated circuit device into the buffer memory, and storing the external data from the buffer memory into the memory block. The external data is read from the memory block and the read external data is stored from the memory block into the buffer memory. The read external data is output from the buffer memory to external of the MML integrated circuit device. The external data may be stored from external of the MML integrated circuit device into the buffer memory by applying external data from external of the MML integrated circuit device to the MML integrated circuit device, replicating the external data a predetermined number of times in the MML integrated circuit device and storing the replicated external data in the buffer memory.

    摘要翻译： MML集成电路装置包括存储块，逻辑电路和缓冲存储器，以及耦合在逻辑电路和缓冲存储器之间的选择电路。 第一选择部分响应于外部数据和逻辑电路，经由缓冲存储器将外部数据或数据从逻辑电路传送到存储块。 因此，MML集成电路器件可以在正常操作模式和测试模式期间使用缓冲存储器访问存储块。 MML集成电路装置还优选地包括耦合在外部数据和选择部分之间的数据扩展部分，以复制外部数据预定次数并将复制的外部数据发送到选择部分。 可以通过将来自MML集成电路装置的外部的外部数据存储到缓冲存储器中，并且将来自缓冲存储器的外部数据存储在存储器块，逻辑电路和缓冲存储器的MML集成电路装置中来检测错误 进入内存块。 从存储器块读取外部数据，读出的外部数据从存储块存储到缓冲存储器中。 读取的外部数据从缓冲存储器输出到MML集成电路器件的外部。 外部数据可以从MML集成电路装置的外部通过将外部数据从MML集成电路装置的外部应用到MML集成电路装置而从MML集成电路装置的外部存储，在MML集成中复制外部数据预定次数 并将复制的外部数据存储在缓冲存储器中。

    BITLINE SENSE AMPLIFIER, MEMORY CORE INCLUDING THE SAME AND METHOD OF SENSING CHARGE FROM A MEMORY CELL
    10.
    发明申请
    BITLINE SENSE AMPLIFIER, MEMORY CORE INCLUDING THE SAME AND METHOD OF SENSING CHARGE FROM A MEMORY CELL 有权
    位线感测放大器，包含其的存储器核心和从存储器单元感测电荷的方法

    公开(公告)号：US20110205822A1

    公开(公告)日：2011-08-25

    申请号：US13006832

    申请日：2011-01-14

    申请人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Jin-Seok Kwak

    发明人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Jin-Seok Kwak

    IPC分类号： G11C7/06 ,  G01R19/00

    CPC分类号： G11C7/12 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4094

    摘要： A bitline sense amplifier includes a pre-sensing unit and an amplification unit. The pre-sensing unit is connected to a first bitline and a second bitline, and is configured to perform a pre-sensing operation by controlling a voltage level of the second bitline based on at least one pre-sensing voltage and variation of a voltage level of the first bitline. The amplification unit is configured to perform a main amplification operation by amplifying a pre-sensed voltage difference based on a first voltage signal and a second voltage signal. The pre-sensed voltage difference indicates a difference between the voltage level of the first bitline and the voltage level of the second bitline after the pre-sensing operation.

    摘要翻译： 位线读出放大器包括预感测单元和放大单元。 预感测单元连接到第一位线和第二位线，并且被配置为通过基于至少一个预感测电压和电压电平的变化来控制第二位线的电压电平来执行预感测操作 的第一个位线。 放大单元被配置为通过基于第一电压信号和第二电压信号放大预感测电压差来执行主放大操作。 预感测电压差表示在预感测操作之后第一位线的电压电平和第二位线的电压电平之间的差。