SUBSCRIBER LINE INTERFACE CIRCUITRY WITH INTEGRATED SERIAL INTERFACES
    2.
    发明申请
    SUBSCRIBER LINE INTERFACE CIRCUITRY WITH INTEGRATED SERIAL INTERFACES 审中-公开
    具有集成串行接口的订户线接口电路

    公开(公告)号:US20100166021A1

    公开(公告)日:2010-07-01

    申请号:US12347991

    申请日:2008-12-31

    IPC分类号: H04J3/06

    CPC分类号: H04J3/1694 H04L7/0008

    摘要: Methods and apparatus for synchronizing communications between a first and a second device include serially communicating a frame having a first format from a first device to a second device, wherein only a frame synchronization timeslot (F1) is asserted. The serially communicated frame having the first format is sampled by the second device until the asserted F1 timeslot is detected. The second device serially communicates a frame having a second format to the first device, wherein only a frame synchronization timeslot (R1) is asserted. The serially communicated frame having the second format is sampled by the first device until the asserted R1 timeslot is detected. The first device establishes synchronization when these steps are successfully repeated. On the second sampling to detect the F1 timeslot, however, the sampling is windowed to less than one timeslot within the expected occurrence of the F1 timeslot.

    摘要翻译: 用于在第一和第二设备之间同步通信的方法和装置包括串行地将具有第一格式的帧从第一设备传送到第二设备,其中只有帧同步时隙(F1)被断言。 具有第一格式的串行通信帧被第二设备采样,直到检测到所确定的F1时隙。 第二设备将具有第二格式的帧串行传送到第一设备,其中只有帧同步时隙(R1)被断言。 具有第二格式的串行通信的帧由第一设备采样,直到检测出有效的R1时隙。 当这些步骤成功重复时,第一个设备建立同步。 然而,在第二次采样以检测F1时隙的情况下,在F1时隙的预期发生期间,采样被窗口化为小于一个时隙。

    Power Supply with Digital Control Loop
    3.
    发明申请
    Power Supply with Digital Control Loop 审中-公开
    带数字控制回路的电源

    公开(公告)号:US20090243578A1

    公开(公告)日:2009-10-01

    申请号:US12060261

    申请日:2008-03-31

    IPC分类号: G05F1/00

    CPC分类号: H02M3/157

    摘要: One embodiment of a power supply apparatus includes a switching regulator generating an output voltage VOUT at an output node from an input voltage VIN at an input node in accordance with a pulse width modulated signal having a nominal frequency of fs. A pulse width modulator provides the pulse width modulated signal in accordance with a pulse control signal. A digital control loop sampling the second voltage to provide an m-bit sampled value at a sampling rate, f1. The digital control loop includes a loop filter providing a filtered value from the sampled value and a delta sigma modulator sampling the filtered value as an n-bit value at a frequency f2 to provide the pulse control signal, wherein m>n.

    摘要翻译: 电源装置的一个实施例包括开关调节器,其根据具有标称频率fs的脉冲宽度调制信号,从输入节点处的输入电压VIN产生输出节点处的输出电压VOUT。 脉冲宽度调制器根据脉冲控制信号提供脉宽调制信号。 数字控制环采样第二电压,以采样速率f1提供m位采样值。 数字控制回路包括环路滤波器,其提供来自采样值的滤波值,并且ΔΣ调制器将滤波后的值采样为频率为f2的n比特值,以提供脉冲控制信号,其中m> n。

    SUBSCRIBER LINE INTERFACE CIRCUITRY WITH INTEGRATED SERIAL INTERFACES
    5.
    发明申请
    SUBSCRIBER LINE INTERFACE CIRCUITRY WITH INTEGRATED SERIAL INTERFACES 审中-公开
    具有集成串行接口的订户线接口电路

    公开(公告)号:US20100166434A1

    公开(公告)日:2010-07-01

    申请号:US12347992

    申请日:2008-12-31

    IPC分类号: H04B10/08

    CPC分类号: H04L12/2885

    摘要: Methods and apparatus for communicating include communicating frames of data at a frequency f1 serially from a first device to a second device using a first unidirectional data line. The frames have a first timeslot allocation of s timeslots. A clock signal having a frequency f2 is generated within the second device, wherein f 2 f 1 ≈ n · s , wherein n>1. The first unidirectional data line is sampled every n clock cycles of the clock signal for a plurality of the timeslots.

    摘要翻译: 用于通信的方法和装置包括使用第一单向数据线将频率f1从第一设备到第二设备串行地传送数据帧。 帧具有时隙的第一时隙分配。 在第二装置内产生具有频率f2的时钟信号,其中f 2 f 1≈n·s,其中n> 1。 在多个时隙的时钟信号的每n个时钟周期对第一单向数据线进行采样。

    Power supply with digital control loop
    6.
    发明授权
    Power supply with digital control loop 有权
    电源带数字控制回路

    公开(公告)号:US08462937B2

    公开(公告)日:2013-06-11

    申请号:US12060263

    申请日:2008-04-01

    IPC分类号: H04M1/00 H04M9/00

    CPC分类号: H04M19/001

    摘要: One embodiment of a power supply apparatus includes a first switcher coupled to provide VOUT from a VSUPPLY. A cascaded second switcher is coupled to provide a subscriber line interface circuit target VBAT from VOUT, wherein the first switcher is placed in one of an active mode and an inactive mode in accordance with a function of VSUPPLY and VBAT, wherein in the active mode  VOUT VSUPPLY  ≥ 1 , wherein in the inactive mode VOUT≈VSUPPLY.

    摘要翻译: 电源设备的一个实施例包括耦合以从VSUPPLY提供VOUT的第一切换器。 级联的第二切换器被耦合以从VOUT提供用户线接口电路目标VBAT,其中根据VSUPPLY和VBAT的功能将第一切换器置于活动模式和非活动模式之一中,其中在活动模式 VOUT VSUPPLY扼= = 1,其中在非活动模式VOUT≈VSUPPLY。

    SUBSCRIBER LINE INTERFACE CIRCUITRY WITH INTEGRATED SERIAL INTERFACES
    7.
    发明申请
    SUBSCRIBER LINE INTERFACE CIRCUITRY WITH INTEGRATED SERIAL INTERFACES 审中-公开
    具有集成串行接口的订户线接口电路

    公开(公告)号:US20100166172A1

    公开(公告)日:2010-07-01

    申请号:US12347986

    申请日:2008-12-31

    IPC分类号: H04M1/00

    摘要: Methods and apparatus for communicating include a first device coupled to a second device with a bi-directional data line and a clock line. Frames of data are serially communicated between the first and second devices on the data line. Each frame is synchronized with a clock signal carried by the clock line. Each frame has a portion allocated to data communicated from the first device to the second device and another portion allocated to data communicated from the second device to the first device.

    摘要翻译: 用于通信的方法和装置包括耦合到具有双向数据线和时钟线的第二装置的第一装置。 在数据线上的第一和第二设备之间串行传送数据帧。 每个帧与由时钟线承载的时钟信号同步。 每个帧具有分配给从第一设备传送到第二设备的数据的部分,以及分配给从第二设备传送到第一设备的数据的另一部分。

    SUBSCRIBER LINE INTERFACE CIRCUITRY WITH INTEGRATED SERIAL INTERFACES
    8.
    发明申请
    SUBSCRIBER LINE INTERFACE CIRCUITRY WITH INTEGRATED SERIAL INTERFACES 审中-公开
    具有集成串行接口的订户线接口电路

    公开(公告)号:US20100166019A1

    公开(公告)日:2010-07-01

    申请号:US12347987

    申请日:2008-12-31

    IPC分类号: H04J3/00

    CPC分类号: H04J3/1694 H04L7/0008

    摘要: Methods and apparatus for communicating include communicating frames of data having a first timeslot allocation of s timeslots serially from a first device to a second device using a first unidirectional data line at a frequency f1. An edge of each frame as a detected edge. A clock signal having a frequency f2 is generated in response to the detected edges, wherein f 2 f 1 ≈ n · s , wherein n>1, wherein the clock signal is maintained substantially synchronous to the detected edges. Frames of data having a second timeslot allocation of s timeslots are communicated serially from the second device to the first device using a second unidirectional data line at the frequency f1 as derived from f2.

    摘要翻译: 用于通信的方法和装置包括使用频率为f1的第一单向数据线将第一时隙的第一时隙分配的数据帧从第一设备串行地传送到第二设备。 每个帧的边缘作为检测到的边缘。 响应于检测到的边缘产生具有频率f2的时钟信号,其中f 2 f 1≈n·s,其中n> 1,其中时钟信号保持与检测到的边缘基本同步。 具有s时隙的第二时隙分配的数据帧,使用从f2导出的频率f1的第二单向数据线,从第二设备串行地传送到第一设备。

    Power Supply with Digital Control Loop
    9.
    发明申请
    Power Supply with Digital Control Loop 有权
    带数字控制回路的电源

    公开(公告)号:US20090245504A1

    公开(公告)日:2009-10-01

    申请号:US12060263

    申请日:2008-04-01

    IPC分类号: H04M9/00

    CPC分类号: H04M19/001

    摘要: One embodiment of a power supply apparatus includes a first switcher coupled to provide VOUT from a VSUPPLY. A cascaded second switcher is coupled to provide a subscriber line interface circuit target VBAT from VOUT, wherein the first switcher is placed in one of an active mode and an inactive mode in accordance with a function of VSUPPLY and VBAT, wherein in the active mode  VOUT VSUPPLY  ≥ 1 , wherein in the inactive mode VOUT≈VSUPPLY.

    摘要翻译: 电源设备的一个实施例包括耦合以从VSUPPLY提供VOUT的第一切换器。 级联的第二切换器被耦合以从VOUT提供用户线接口电路目标VBAT,其中根据VSUPPLY和VBAT的功能将第一切换器置于活动模式和非活动模式之一中,其中在活动模式< maths id =“MATH-US-00001”num =“00001”> mi> > 其中处于非活动模式VOUT≈VSUPPLY。