Voltage regulator with adaptive control
    2.
    发明授权
    Voltage regulator with adaptive control 有权
    具有自适应控制的电压调节器

    公开(公告)号:US09509214B2

    公开(公告)日:2016-11-29

    申请号:US13997712

    申请日:2012-05-01

    CPC classification number: H02M3/10 H02M3/157 H02M2001/0025 H02M2003/1566

    Abstract: Generally, this disclosure describes an apparatus, systems and methods for adaptively controlling a voltage regulator. The apparatus may include a differencing circuit configured to generate an error signal based on a difference between a reference voltage and the output voltage of the voltage regulator; a proportional control circuit coupled to the differencing circuit, the proportional control circuit configured to generate a control signal proportional to the error signal; a derivative control circuit coupled to the differencing circuit, the derivative control circuit configured to generate a control signal based on the derivative of the error signal; a summer circuit coupled to the proportional control circuit and the derivative control circuit, the summer circuit configured to sum the proportional control signal and the derivative control signal; a PWM signal generator circuit coupled to the summer circuit, the PWM generator circuit configured to adjust the PWM modulation based on the summed control signal; and a state monitor circuit configured to monitor the state of the output voltage and perform a gain adjustment on the proportional control signal and the derivative control signal based on the monitored state.

    Abstract translation: 通常,本公开描述了用于自适应地控制电压调节器的装置,系统和方法。 该装置可以包括差分电路,其被配置为基于参考电压和电压调节器的输出电压之间的差产生误差信号; 比例控制电路,其耦合到所述差分电路,所述比例控制电路被配置为产生与所述误差信号成比例的控制信号; 微分控制电路,被配置为基于误差信号的导数产生控制信号;微分控制电路, 夏季电路,其耦合到所述比例控制电路和所述微分控制电路,所述加法电路被配置为对所述比例控制信号和所述微分控制信号进行求和; PWM信号发生器电路,其耦合到所述加法电路,所述PWM发生器电路被配置为基于所述相加的控制信号来调整所述PWM调制; 以及状态监视电路,其被配置为基于所监视的状态监视所述输出电压的状态并对所述比例控制信号和所述微分控制信号执行增益调整。

    Power management in transceivers
    5.
    发明授权
    Power management in transceivers 有权
    收发器电源管理

    公开(公告)号:US08742843B2

    公开(公告)日:2014-06-03

    申请号:US13330412

    申请日:2011-12-19

    Abstract: Various embodiments are directed to apparatuses and methods to reduce average power dissipation in transceiver stages such as power amplifiers and low noise amplifiers (LNAs) that process signals of varying output amplitudes. Power dissipation may be reduced by varying the supply voltage in sympathy with the amplitude of the signal and/or the stage current density which may also be varied in sympathy with the signal amplitude.

    Abstract translation: 各种实施例涉及减少收发机级中的平均功率耗散的装置和方法,例如功率放大器和处理变化的输出幅度的信号的低噪声放大器(LNA)。 通过改变与信号幅度和/或阶段电流密度同步的电源电压,可以减少功率消耗,这也可以在与信号幅度相同的情况下变化。

    Successive approximation analog-to-digital conversion with gain control for tuners
    6.
    发明授权
    Successive approximation analog-to-digital conversion with gain control for tuners 有权
    用于调谐器的增益控制的逐次近似模数转换

    公开(公告)号:US08730074B1

    公开(公告)日:2014-05-20

    申请号:US13740472

    申请日:2013-01-14

    CPC classification number: H03M1/183

    Abstract: A method and system for implementing a gain control with fine resolution and minimal additional circuitry. The fine digital gain control may be deployed in conjunction with a coarse switched gain at the front end of a sampling receiver. The fine digital gain control mechanism is configured to receive an input signal and moderate gains applied to the received input signal. The output of a low noise amplifier (LNA) is connected to a switched attenuator which provides fine gain stepped gain control. The output of this stage is connected to the switch stage whose output is connected to a charge redistribution successive approximation register digital-to-analog converter (SAR ADC) configured to convert an analog waveform into a digital representation.

    Abstract translation: 一种用于实现具有精细分辨率和最小额外电路的增益控制的方法和系统。 精细的数字增益控制可以结合在采样接收器的前端处的粗略的开关增益来部署。 精细数字增益控制机构被配置为接收输入信号并且适中的增益被施加到所接收的输入信号。 低噪声放大器(LNA)的输出连接到提供精细增益阶梯增益控制的开关衰减器。 该级的输出连接到开关级,其输出端连接到配置为将模拟波形转换为数字表示的电荷再分配逐次逼近寄存器数模转换器(SAR ADC)。

    Methods and systems to compensate IQ imbalance in wideband zero-if tuners
    7.
    发明授权
    Methods and systems to compensate IQ imbalance in wideband zero-if tuners 有权
    补偿宽带零无功调谐器智能失衡的方法和系统

    公开(公告)号:US08385457B2

    公开(公告)日:2013-02-26

    申请号:US12565381

    申请日:2009-09-23

    Abstract: Methods and systems to compensate IQ imbalances in a tuner system, including relatively wideband ZIF tuner systems and tuner systems having substantially linear frequency dependent phase imbalance, where a one-tap compensation element may be utilized to compensate frequency dependent phase imbalance. A two tone probe may be applied in controlled loop-back modes, and resultant baseband components may be used to determine a straight line from which to determine compensation. The probe may include a Multi-Media over Coax Alliance (MoCA) Type 2 probe. Compensation parameters may be determined as fixed or non-adaptive compensation parameters in a digital domain and may be applied at baseband. One or more compensation values may be determined in a fixed point circuit.

    Abstract translation: 用于补偿调谐器系统中的IQ不平衡的方法和系统,包括相对宽带的ZIF调谐器系统和具有基本线性的频率相关相位不平衡的调谐器系统,其中可以利用单抽头补偿元件来补偿频率相关的相位不平衡。 双音调探针可以以受控的环回模式应用,并且所得到的基带分量可用于确定从其确定补偿的直线。 探头可以包括多媒体同轴联盟(MoCA)2型探头。 补偿参数可以被确定为数字域中的固定或非自适应补偿参数,并且可以在基带处应用。 可以在固定点电路中确定一个或多个补偿值。

    Alignment of channel filters for multiple-tuner apparatuses
    8.
    发明申请
    Alignment of channel filters for multiple-tuner apparatuses 有权
    多调谐器设备的通道滤波器对齐

    公开(公告)号:US20110019785A1

    公开(公告)日:2011-01-27

    申请号:US12460811

    申请日:2009-07-24

    CPC classification number: H04B17/11

    Abstract: Apparatuses, systems, and methods that align channel filters for dual tuners are disclosed. An embodiment may comprise an IC having two tuners. Each tuner may have a low-noise amplifier, a mixer with a local oscillator, and channel filter. To perform a channel filter alignment, a bandwidth controller may cross-couple the local oscillator of each tuner to the input of the mixer of the opposite tuner. The bandwidth controller may adjust the frequencies of the local oscillators to produce different configuration tone frequencies at the outputs of the mixers, which are inputs to the channel filters. The bandwidth controller may then determine an amplitude difference between two separate measurements of a channel filter output and, based on a comparison of the measurements with predicted values, increment or decrement the filter bandwidth for each tuner and store parameters for the channel filters which create the largest signal amplitudes.

    Abstract translation: 公开了用于对准双调谐器的信道滤波器的装置,系统和方法。 实施例可以包括具有两个调谐器的IC。 每个调谐器可以具有低噪声放大器,具有本地振荡器的混频器和信道滤波器。 为了执行信道滤波器对准,带宽控制器可以将每个调谐器的本地振荡器交叉到相对调谐器的混频器的输入端。 带宽控制器可以调整本地振荡器的频率,以在混频器的输出端产生不同的配置音频率,这些是频道滤波器的输入。 然后,带宽控制器可以确定信道滤波器输出的两个单独测量之间的幅度差,并且基于测量与预测值的比较,增加或减少每个调谐器的滤波器带宽,并存储用于创建 最大信号幅度。

    PULSE GENERATOR, OPTICAL DISK WRITER AND TUNER
    9.
    发明申请
    PULSE GENERATOR, OPTICAL DISK WRITER AND TUNER 有权
    脉冲发生器,光盘写波器和调谐器

    公开(公告)号:US20070047416A1

    公开(公告)日:2007-03-01

    申请号:US11466242

    申请日:2006-08-22

    Abstract: A pulse generator is provided for generating pulses with a selectable variable width and/or delay. The pulse generator comprises an oscillator and a selecting arrangement for selecting how many of a first group of delay elements are connected in series for delaying the oscillator signal. Identical delay elements are connected in series to form a second group. A measuring circuit repeatedly measures the delay provided by the second group, for example providing output pulses whose width or duration is equal to the delay. A reference pulse generator generates a series of reference pulses, each of which is a predetermined fraction of the oscillator period. A control circuit compares the measurement and reference pulses to generate an error signal that is fed back to timing delay control inputs of all the delay elements such that the widths of the measurement and reference pulses are made substantially equal to each other.

    Abstract translation: 提供脉冲发生器用于产生具有可选择的可变宽度和/或延迟的脉冲。 脉冲发生器包括振荡器和选择装置,用于选择串联连接多少第一组延迟元件以延迟振荡器信号。 相同的延迟元件串联连接以形成第二组。 测量电路重复测量由第二组提供的延迟,例如提供其宽度或持续时间等于延迟的输出脉冲。 参考脉冲发生器产生一系列参考脉冲,每个参考脉冲是振荡器周期的预定分数。 控制电路比较测量和参考脉冲以产生反馈到所有延迟元件的定时延迟控制输入的误差信号,使得测量和参考脉冲的宽度彼此基本相等。

    System for analog to digital conversion with improved spurious free dynamic range
    10.
    发明授权
    System for analog to digital conversion with improved spurious free dynamic range 有权
    具有改进的无杂散动态范围的模数转换系统

    公开(公告)号:US09325339B2

    公开(公告)日:2016-04-26

    申请号:US13995211

    申请日:2012-05-01

    CPC classification number: H03M1/124 H03B28/00 H03H7/01 H03M1/0626 H03M1/1215

    Abstract: Generally, this disclosure describes an apparatus, systems and methods for analog to digital conversion with improved spurious free dynamic range. The system includes a segmented ADC circuit with a plurality of interleaved ADC segments, the segmented ADC circuit configured to generate a digital signal including a channel with an associated channel frequency; a frequency down-converter circuit coupled to the segmented ADC circuit, the frequency down-converter circuit configured to frequency shift the digital signal by a frequency offset; a spur frequency prediction circuit coupled to the frequency down-converter circuit, the spur frequency prediction circuit configured to predict frequencies of spurs generated by the ADC segments, the prediction based on the number of ADC segments and based on the sampling rate of the digital signal; the spur frequency prediction circuit further configured to generate the frequency offset based on the predicted spur frequencies and based on a frequency band of the channel; and a filter circuit coupled to the frequency down-converter circuit, the filter circuit configured to remove one or more of the spurs from the frequency shifted digital signal to generate a filtered signal.

    Abstract translation: 通常,本公开描述了具有改进的无杂散动态范围的用于模数转换的装置,系统和方法。 该系统包括具有多个交错ADC段的分段ADC电路,分段ADC电路被配置为生成包括具有相关信道频率的信道的数字信号; 所述降频转换器电路被耦合到所述分段ADC电路,所述降频转换器电路被配置为使所述数字信号频率偏移频率偏移; 耦合到所述降频转换器电路的杂散频率预测电路,所述杂散频率预测电路被配置为预测由所述ADC段产生的杂散的频率,所述预测基于所述ADC段的数量,并且基于所述数字信号的采样率 ; 所述杂音频率预测电路还被配置为基于所述预测的杂散频率并且基于所述信道的频带来生成所述频率偏移; 以及耦合到所述降频转换器电路的滤波器电路,所述滤波器电路被配置为从所述频移数字信号中去除所述杂波中的一个或多个以产生经滤波的信号。

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