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公开(公告)号：US20130328400A1
公开(公告)日：2013-12-12
申请号：US13592553
申请日：2012-08-23
IPC分类号： H02J4/00
CPC分类号： H02J5/00 , G06F1/263 , G06F1/28 , G06F1/305 , Y10T307/50 , Y10T307/62
摘要： A redundant path power subsystem comprises a plurality of phase regulators in a multi-phase power converter. The plurality of phase regulators comprises at least N+2 phase regulators. N phases are sufficient to serve an electrical load coupled with the redundant path power subsystem. The redundant path power subsystem also comprises a plurality of power supplies, and a plurality of input and control paths between the plurality of power supplies and the plurality of phase regulators. The plurality of input and control paths comprises a plurality of multiplexing logic devices and a plurality of phase controllers. The plurality of phase controllers is operable to control the plurality of phase regulators. The plurality of multiplexing logic devices is operable to multiplex control signals from the plurality of power supplies and a microprocessor for the plurality of phase controllers.
摘要翻译： 冗余路径功率子系统包括多相功率转换器中的多个相位调节器。 多个相位调节器至少包括N + 2相位调节器。 N个相位足以用于与冗余路径功率子系统耦合的电负载。 冗余路径功率子系统还包括多个电源，以及多个电源和多个相位调节器之间的多个输入和控制路径。 多个输入和控制路径包括多个复用逻辑器件和多个相位控制器。 多个相位控制器可操作以控制多个相位调节器。 多个复用逻辑器件可操作用于复用来自多个电源的控制信号和多个相位控制器的微处理器。
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公开(公告)号：US09030047B2
公开(公告)日：2015-05-12
申请号：US13492403
申请日：2012-06-08
CPC分类号： H02J5/00 , G06F1/263 , G06F1/28 , G06F1/305 , Y10T307/50 , Y10T307/62
摘要： A redundant path power subsystem comprises a plurality of phase regulators in a multi-phase power converter. The plurality of phase regulators comprises at least N+2 phase regulators. N phases are sufficient to serve an electrical load coupled with the redundant path power subsystem. The redundant path power subsystem also comprises a plurality of power supplies, and a plurality of input and control paths between the plurality of power supplies and the plurality of phase regulators. The plurality of input and control paths comprises a plurality of multiplexing logic devices and a plurality of phase controllers. The plurality of phase controllers is operable to control the plurality of phase regulators. The plurality of multiplexing logic devices is operable to multiplex control signals from the plurality of power supplies and a microprocessor for the plurality of phase controllers.
摘要翻译： 冗余路径功率子系统包括多相功率转换器中的多个相位调节器。 多个相位调节器至少包括N + 2相位调节器。 N个相位足以用于与冗余路径功率子系统耦合的电负载。 冗余路径功率子系统还包括多个电源，以及多个电源和多个相位调节器之间的多个输入和控制路径。 多个输入和控制路径包括多个复用逻辑器件和多个相位控制器。 多个相位控制器可操作以控制多个相位调节器。 多个复用逻辑器件可操作用于复用来自多个电源的控制信号和多个相位控制器的微处理器。
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公开(公告)号：US20130329474A1
公开(公告)日：2013-12-12
申请号：US13492403
申请日：2012-06-08
IPC分类号： H02H7/122
CPC分类号： H02J5/00 , G06F1/263 , G06F1/28 , G06F1/305 , Y10T307/50 , Y10T307/62
摘要： A redundant path power subsystem comprises a plurality of phase regulators in a multi-phase power converter. The plurality of phase regulators comprises at least N+2 phase regulators. N phases are sufficient to serve an electrical load coupled with the redundant path power subsystem. The redundant path power subsystem also comprises a plurality of power supplies, and a plurality of input and control paths between the plurality of power supplies and the plurality of phase regulators. The plurality of input and control paths comprises a plurality of multiplexing logic devices and a plurality of phase controllers. The plurality of phase controllers is operable to control the plurality of phase regulators. The plurality of multiplexing logic devices is operable to multiplex control signals from the plurality of power supplies and a microprocessor for the plurality of phase controllers.
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4.发明授权公开(公告)号：US07353308B2
公开(公告)日：2008-04-01
申请号：US11254577
申请日：2005-10-20
申请人： Daniel J. Barus , Eileen M. Behrendt , Jeffrey R. Biamonte , Raymond J. Harrington , Timothy M. Trifilo
发明人： Daniel J. Barus , Eileen M. Behrendt , Jeffrey R. Biamonte , Raymond J. Harrington , Timothy M. Trifilo
IPC分类号： G06F13/00
CPC分类号： G06F13/4077 , H04L5/16
摘要： In a bi-directional, self-synchronous bus for communication between semiconductor devices, a logic delay is provided as a flag to a state machine control for indicating that the bus is making a transition from a low to a high state. The logic delay causes the bus to adaptively idle until the bus settles, making it amenable for a wide variety of bus sizes and topologies. In this way, oscillation of the bus is avoided without slowing the speed of the state machine clock.
摘要翻译： 在用于半导体器件之间的通信的双向自同步总线中，提供逻辑延迟作为状态机控制的标志，用于指示总线正在从低状态转变为高状态。 逻辑延迟导致总线自适应空闲，直到总线稳定，使其适用于各种总线大小和拓扑。 以这种方式，避免了总线的振荡，而不会降低状态机时钟的速度。
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5.发明授权公开(公告)号：US07057414B2
公开(公告)日：2006-06-06
申请号：US10752956
申请日：2004-01-07
申请人： Daniel J. Barus , Eileen M. Behrendt , Jeffrey R. Biamonte , Raymond J. Harrington , Timothy M. Trifilo
发明人： Daniel J. Barus , Eileen M. Behrendt , Jeffrey R. Biamonte , Raymond J. Harrington , Timothy M. Trifilo
IPC分类号： H03K19/173
CPC分类号： G06F13/4077 , H04L5/16
摘要： In a bi-directional, self-synchronous bus for communication between semiconductor devices, a logic delay is provided as a flag to a state machine control for indicating that the bus is making a transition from a low to a high state. The logic delay causes the bus to adaptively idle until the bus settles, making it amenable for a wide variety of bus sizes and topologies. In this way, oscillation of the bus is avoided without slowing the speed of the state machine clock.
摘要翻译： 在用于半导体器件之间的通信的双向自同步总线中，提供逻辑延迟作为状态机控制的标志，用于指示总线正在从低状态转变为高状态。 逻辑延迟导致总线自适应空闲，直到总线稳定，使其适用于各种总线大小和拓扑。 以这种方式，避免了总线的振荡，而不会降低状态机时钟的速度。
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公开(公告)号：US09298241B2
公开(公告)日：2016-03-29
申请号：US13592553
申请日：2012-08-23
CPC分类号： H02J5/00 , G06F1/263 , G06F1/28 , G06F1/305 , Y10T307/50 , Y10T307/62
摘要： A redundant path power subsystem comprises a plurality of phase regulators in a multi-phase power converter. The plurality of phase regulators comprises at least N+2 phase regulators. N phases are sufficient to serve an electrical load coupled with the redundant path power subsystem. The redundant path power subsystem also comprises a plurality of power supplies, and a plurality of input and control paths between the plurality of power supplies and the plurality of phase regulators. The plurality of input and control paths comprises a plurality of multiplexing logic devices and a plurality of phase controllers. The plurality of phase controllers is operable to control the plurality of phase regulators. The plurality of multiplexing logic devices is operable to multiplex control signals from the plurality of power supplies and a microprocessor for the plurality of phase controllers.
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7.发明授权Autonomous, scalable, digital system for emulation of wired-or hardware connection 有权自动，可扩展的数字系统，用于仿真有线或硬件连接公开(公告)号：US08812287B2
公开(公告)日：2014-08-19
申请号：US13022647
申请日：2011-02-08
申请人： Daniel J Barus
发明人： Daniel J Barus
CPC分类号： G06F13/105 , G06F1/04 , G06F11/261 , G06F17/50
摘要： A method and device for preserving the wired-OR nature of the clock signal connection between two devices without a direct analog connection between the lines and in an infinitely scalable fashion. The method includes detecting a logic state at a first connector and a second connector and driving an appropriate connector of the device to an active state in response to determining that a connector is driving an active state. The device includes first and second connectors for communicating logic states and driving active states in response to detected logic states.
摘要翻译： 一种用于在两个设备之间保持时钟信号连接的有线性质的方法和设备，而不需要线路之间的直接模拟连接并且以无限可伸缩的方式。 该方法包括响应于确定连接器正在驱动活动状态，检测在第一连接器和第二连接器处的逻辑状态并将设备的适当连接器驱动到活动状态。 该装置包括用于响应于检测到的逻辑状态传送逻辑状态和驱动有效状态的第一和第二连接器。
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8.发明申请Autonomous, Scalable, Digital System For Emulation of Wired-Or Hardware Connection 有权自动，可扩展，数字系统用于有线或硬件连接的仿真公开(公告)号：US20120203537A1
公开(公告)日：2012-08-09
申请号：US13022647
申请日：2011-02-08
申请人： Daniel J. Barus
发明人： Daniel J. Barus
IPC分类号： G06F9/455
CPC分类号： G06F13/105 , G06F1/04 , G06F11/261 , G06F17/50
摘要： A method and device for preserving the wired-OR nature of the clock signal connection between two devices without a direct analog connection between the lines and in an infinitely scalable fashion. The method includes detecting a logic state at a first connector and a second connector and driving an appropriate connector of the device to an active state in response to determining that a connector is driving an active state. The device includes first and second connectors for communicating logic states and driving active states in response to detected logic states.
摘要翻译： 一种用于在两个设备之间保持时钟信号连接的有线性质的方法和设备，而不需要线路之间的直接模拟连接并且以无限可伸缩的方式。 该方法包括响应于确定连接器正在驱动活动状态，检测在第一连接器和第二连接器处的逻辑状态并将设备的适当连接器驱动到活动状态。 该装置包括用于响应于检测到的逻辑状态传送逻辑状态和驱动有效状态的第一和第二连接器。
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公开(公告)号：US06876229B1
公开(公告)日：2005-04-05
申请号：US10668488
申请日：2003-09-23
IPC分类号： H04L5/14 , H03K19/0175
CPC分类号： H04L5/1423
摘要： A communication system for establishing bidirectional, asynchronous communication between a first device and a second device. The system includes first asynchronous encoder logic and second asynchronous encoder logic for controlling the state of the communication system such that bi-directional communication is enabled without a direction control line.
摘要翻译： 一种用于在第一设备和第二设备之间建立双向异步通信的通信系统。 该系统包括用于控制通信系统的状态的第一异步编码器逻辑和第二异步编码器逻辑，使得在没有方向控制线的情况下启用双向通信。
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