公开(公告)号：US5411907A

公开(公告)日：1995-05-02

申请号：US937735

申请日：1992-09-01

Applicant: Chue-San Yoo ,  Jyh-Min Tsaur ,  Chong-Shi Chen ,  Pin-Nan Tseng

Inventor： Chue-San Yoo ,  Jyh-Min Tsaur ,  Chong-Shi Chen ,  Pin-Nan Tseng

IPC: H01L21/336 ,  H01L21/265

CPC classification number: H01L29/6659

Abstract: A method is described for fabricating a lightly doped drain MOS FET integrated circuit device with a peeling-free metal silicide gate electrode continues by annealing the gate oxide, the polysilicon layer and the metal silicide layer using a furnace process at a temperature more than about 920.degree. C. and for a time of less than about 40 minutes. A pattern of lightly doped regions is formed in the substrate by ion implantation using the structures as the mask. A low temperature silicon dioxide layer is blanket deposited over the surfaces of the structure. The pattern of lightly doped regions is driven in while maintaining the low temperature silicon oxide over the metal silicide layer by annealing at a temperature of more than about 920.degree. C. The blanket layer is etched to form a dielectric spacer structure upon the sidewalls of each of the gate electrode structures and over the adjacent portions of the substrate, and to remove the silicon oxide layer from the top surfaces of metal silicide layer. Heavily doped regions are formed. A passivation layer which includes a silicon oxide layer and a thicker dielectric layer is formed over the structures. The heavily doped regions are annealed to drivein the impurities at a temperature of more than about 920.degree. C. while maintaining said passivation layer over said metal silicide layer.

Abstract translation: 描述了一种用于制造具有无剥离金属硅化物栅电极的轻掺杂漏极MOS FET集成电路器件的方法，其通过使用炉法在大于约920的温度下退火栅极氧化物，多晶硅层和金属硅化物层 并且时间小于约40分钟。 通过使用该结构作为掩模的离子注入在衬底中形成轻掺杂区域的图案。 低温二氧化硅层被覆盖在该结构的表面上。 驱动轻掺杂区域的图案，同时通过在超过约920℃的温度下退火，在金属硅化物层上保持低温氧化硅的同时，蚀刻覆盖层以在每个侧壁上形成电介质间隔物结构 的栅极电极结构和衬底的相邻部分之上，并从金属硅化物层的顶表面去除氧化硅层。 形成重掺杂区域。 在结构上形成包括氧化硅层和较厚电介质层的钝化层。 重掺杂区域被退火以在大于约920℃的温度下驱动杂质，同时将所述钝化层保持在所述金属硅化物层上。