公开(公告)号：US08438529B1

公开(公告)日：2013-05-07

申请号：US13585854

申请日：2012-08-15

申请人： Ya-Ling Huang ,  Ling-Ling Shen ,  Chia-Nan Pai ,  Shou-Kuo Hsu

发明人： Ya-Ling Huang ,  Ling-Ling Shen ,  Chia-Nan Pai ,  Shou-Kuo Hsu

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A computer-based method and a computing device for checking signal transmission lines of a printed circuit board (PCB) layout are provided. The computing device identifies differential pairs in a currently run PCB layout according to an information file for the currently run PCB layout, checks whether any signal transmission line is routed between switching vias of each differential pair according to the information file for the currently run PCB layout, and displays a routing error window to display information of each misrouted signal transmission line.

摘要翻译： 提供了一种用于检查印刷电路板（PCB）布局的信号传输线的基于计算机的方法和计算装置。 根据当前运行的PCB布局的信息文件，计算设备根据当前运行的PCB布局的信息文件识别当前运行的PCB布局中的差分对，根据当前运行的PCB布局的信息文件，检查每个差分对的切换通孔之间是否有任何信号传输线路由 ，并显示路由错误窗口以显示每条错误路由的信号传输线路的信息。

公开(公告)号：US20120331437A1

公开(公告)日：2012-12-27

申请号：US13407768

申请日：2012-02-29

申请人： CHIA-NAN PAI ,  SHOU-KUO HSU ,  YA-LING HUANG

发明人： CHIA-NAN PAI ,  SHOU-KUO HSU ,  YA-LING HUANG

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： In a method for checking layout of a printed circuit board (PCB) using an electronic device, a signal line is selected from a layout diagram of the PCB. The method searches for signal lines which have an acute angle when deviating from a straight line in the layout diagram of the PCB. The method further locates attribute data of the searched signal lines in the layout diagram of the PCB, and displays the attribute data of the searched signal lines on a display device of the electronic device.

摘要翻译： 在使用电子设备检查印刷电路板（PCB）的布局的方法中，从PCB的布局图中选择信号线。 该方法搜索在PCB布局图中偏离直线时具有锐角的信号线。 该方法进一步在PCB的布局图中定位搜索到的信号线的属性数据，并将所搜索的信号线的属性数据显示在电子设备的显示装置上。

公开(公告)号：US20120247825A1

公开(公告)日：2012-10-04

申请号：US13288144

申请日：2011-11-03

申请人： MING WEI ,  CHIA-NAN PAI ,  NING LI ,  SHOU-KUO HSU

发明人： MING WEI ,  CHIA-NAN PAI ,  NING LI ,  SHOU-KUO HSU

IPC分类号： H05K1/11

CPC分类号： H05K1/0222 ,  H05K1/0245 ,  H05K2201/09618

摘要： A printed circuit board (PCB) includes a top signal layer, a bottom signal layer, a ground layer, a plurality of vias, and at least two ground vias. Both the top signal layer and the bottom signal layer include at least one protection line. The ground layer is located between the top signal layer and the bottom signal layer. The at least two ground vias extend through the PCB and are located adjacent to the vias on the PCB. The at least two ground vias are electrically connected to the ground layer to conduct noise signals, and the at least two ground vias are electrically connected by the protection lines to insulate noise signals.

摘要翻译： 印刷电路板（PCB）包括顶部信号层，底部信号层，接地层，多个通孔和至少两个接地通孔。 顶部信号层和底部信号层都包括至少一个保护线。 接地层位于顶层信号层和底层信号层之间。 至少两个接地通孔延伸穿过PCB，并且位于邻近PCB上的通孔处。 所述至少两个接地通孔电连接到接地层以传导噪声信号，并且所述至少两个接地通孔由保护线电连接以绝缘噪声信号。

公开(公告)号：US20120241201A1

公开(公告)日：2012-09-27

申请号：US13107950

申请日：2011-05-15

申请人： HUA-LI ZHOU ,  CHIA-NAN PAI ,  SHOU-KUO HSU

发明人： HUA-LI ZHOU ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC分类号： H05K1/09

CPC分类号： H05K1/025 ,  H05K1/024 ,  H05K1/0245 ,  H05K2201/09727

摘要： A circuit board includes a substrate and a copper layer positioned on the substrate. The copper layer includes a BGA area and a non-BGA area, and includes traces. The widths of the traces in the BGA area are smaller than the widths of the traces in the non-BGA area, the dielectric coefficient of the substrate in the BGA area is greater than the dielectric coefficient of the substrate in the non-BGA area for keeping the impedance of the traces consistent in the BGA area and in the non-BGA area.

摘要翻译： 电路板包括基板和位于基板上的铜层。 铜层包括BGA区域和非BGA区域，并且包括痕迹。 BGA区域中的迹线的宽度小于非BGA区域中的迹线的宽度，BGA区域中的衬底的介电系数大于非BGA区域中衬底的介电系数， 保持BGA区域和非BGA区域的轨迹阻抗一致。

公开(公告)号：US20120234590A1

公开(公告)日：2012-09-20

申请号：US13095853

申请日：2011-04-28

申请人： MING WEI ,  NING LI ,  CHIA-NAN PAI ,  SHOU-KUO HSU

发明人： MING WEI ,  NING LI ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC分类号： H05K1/11

CPC分类号： H05K1/0251 ,  H05K1/115

摘要： A printed circuit board includes first to sixth layers, and first to third traces. The first trace is arranged on the first layer. The second trace is arranged on the third layer. The third trace is arranged on the sixth layer. The second trace is electrically connected to the first trace through a first vertical interconnection access (via). The second trace is electrically connected to the third trace through a second via.

摘要翻译： 印刷电路板包括第一至第六层以及第一至第三迹线。 第一个轨迹排列在第一层。 第二个轨迹排列在第三层上。 第三条线排列在第六层。 第二迹线通过第一垂直互连接入（via）与第一迹线电连接。 第二迹线通过第二通孔电连接到第三迹线。

公开(公告)号：US08146048B2

公开(公告)日：2012-03-27

申请号：US12699839

申请日：2010-02-03

申请人： Han-Long Chen ,  Chia-Nan Pai ,  Shou-Kuo Hsu

发明人： Han-Long Chen ,  Chia-Nan Pai ,  Shou-Kuo Hsu

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A system and method for removing T-point elements with unused stubs from a printed circuit board (PCB) layout design obtains each signal line including one or more T-point elements in the PCB layout design, divides the obtained signal line into a plurality of lines according to the one or more T-point elements with unused stubs, and obtains properties of each of the plurality of lines. The system and method further deletes the original layout of the signal line and reconnects the plurality of lines according to the properties of each of the plurality of lines to generate a reconnected signal line, and outputs the reconnected signal line on a display device.

摘要翻译： 用于从印刷电路板（PCB）布局设计中去除具有未使用的短截线的T点元件的系统和方法获得在PCB布局设计中包括一个或多个T点元件的每条信号线，将获得的信号线分成多个 根据具有未使用短截线的一个或多个T点元素的线，并且获得多条线中的每一条的属性。 该系统和方法进一步删除信号线的原始布局，并根据多条线中的每条线路的属性重新连接多条线路，以产生重新连接的信号线，并将重新连接的信号线输出到显示设备上。

公开(公告)号：US20120026707A1

公开(公告)日：2012-02-02

申请号：US12872652

申请日：2010-08-31

申请人： SHI-PIAO LUO ,  CHIA-NAN PAI ,  SHOU-KUO HSU

发明人： SHI-PIAO LUO ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC分类号： H05K7/00

CPC分类号： H05K1/0245 ,  H05K1/0243

摘要： A printed circuit board includes first and second layers, a control chip, bonding pads, and several electronic elements. The bonding pads can be selectively applied to interconnect the first and second layers, and the control chip with any of the electronic elements in a simple layout.

摘要翻译： 印刷电路板包括第一层和第二层，控制芯片，焊盘和几个电子元件。 可以选择性地施加接合焊盘以以简单的布局将第一层和第二层以及控制芯片与任何电子元件互连。

公开(公告)号：US07843281B2

公开(公告)日：2010-11-30

申请号：US11838238

申请日：2007-08-14

申请人： Shou-Kuo Hsu ,  Chia-Nan Pai ,  Hsiao-Chuan Tu

发明人： Shou-Kuo Hsu ,  Chia-Nan Pai ,  Hsiao-Chuan Tu

IPC分类号： H03H7/38

CPC分类号： H05K1/0246 ,  H05K1/0237 ,  H05K2201/09254 ,  H05K2201/10022

摘要： A circuit topology for multiple loads is provided. In an embodiment, the circuit topology includes a driving terminal (50), a first node (A), a first receiving terminal (10), and a second receiving terminal (20). The driving terminal is coupled to the first node via a main transmission line (11), the first node is respectively coupled to the first and second receiving terminals via a first branch transmission line (13) and a second branch transmission line (12). A first resistor (R2) is mounted on the second branch transmission line, a distance the signal travels from the driving terminal to the second receiving terminal via the main transmission line and the second branch transmission line is greater than a distance the signal travels from the driving terminal to the first receiving terminal via the main transmission and the first branch transmission line.

摘要翻译： 提供了多个负载的电路拓扑。 在一个实施例中，电路拓扑包括驱动终端（50），第一节点（A），第一接收终端（10）和第二接收终端（20）。 驱动终端经由主传输线（11）耦合到第一节点，第一节点经由第一分支传输线（13）和第二分支传输线（12）分别耦合到第一和第二接收终端。 第一电阻器（R2）安装在第二分支传输线上，信号经由主传输线从驱动端到第二接收端的距离，第二分支传输线大于信号从 驱动终端通过主传输和第一分支传输线路连接到第一接收终端。

公开(公告)号：US20090065238A1

公开(公告)日：2009-03-12

申请号：US11957416

申请日：2007-12-15

申请人： CHIEN-HUNG LIU ,  SHOU-KUO HSU ,  CHIA-NAN PAI

发明人： CHIEN-HUNG LIU ,  SHOU-KUO HSU ,  CHIA-NAN PAI

IPC分类号： H05K1/00

CPC分类号： H05K1/0245 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09672

摘要： An exemplary PCB includes a first reference layer, a first signal layer, a second signal layer, and a third signal layer in that order, a first differential pair is arranged in the first signal layer in edge-coupled structure and references the first reference layer, a distance between the first signal layer and the second signal layer is greater than a distance between the first reference layer and the first signal layer, a second differential pair is arranged in the second signal layer and the third signal layer in broad-coupled structure. The PCB has a high density layout of transmission lines.

摘要翻译： 示例性PCB包括第一参考层，第一信号层，第二信号层和第三信号层，第一差分对以边缘耦合结构布置在第一信号层中，并参考第一参考层 第一信号层和第二信号层之间的距离大于第一参考层和第一信号层之间的距离，第二差分对被布置在第二信号层中，第三信号层以广泛耦合结构 。 PCB具有传输线高密度布局。

公开(公告)号：US20080116994A1

公开(公告)日：2008-05-22

申请号：US11838238

申请日：2007-08-14

申请人： SHOU-KUO HSU ,  CHIA-NAN PAI ,  HSIAO-CHUAN TU

发明人： SHOU-KUO HSU ,  CHIA-NAN PAI ,  HSIAO-CHUAN TU

IPC分类号： H03H7/38

CPC分类号： H05K1/0246 ,  H05K1/0237 ,  H05K2201/09254 ,  H05K2201/10022

摘要： A circuit topology for multiple loads is provided. In an embodiment, the circuit topology includes a driving terminal (50), a first node (A), a first receiving terminal (10), and a second receiving terminal (20). The driving terminal is coupled to the first node via a main transmission line (11), the first node is respectively coupled to the first and second receiving terminals via a first branch transmission line (13) and a second branch transmission line (12). A first resistor (R2) is mounted on the second branch transmission line, a distance the signal travels from the driving terminal to the second receiving terminal via the main transmission line and the second branch transmission line is greater than a distance the signal travels from the driving terminal to the first receiving terminal via the main transmission and the first branch transmission line.

摘要翻译： 提供了多个负载的电路拓扑。 在一个实施例中，电路拓扑包括驱动终端（50），第一节点（A），第一接收终端（10）和第二接收终端（20）。 驱动终端经由主传输线（11）耦合到第一节点，第一节点经由第一分支传输线（13）和第二分支传输线（12）分别耦合到第一和第二接收终端。 第一电阻器（R 2）安装在第二分支传输线上，信号经由主传输线从驱动端到达第二接收端的距离，第二分支传输线大于信号从 所述驱动终端经由所述主发送和所述第一分支传输线路发送到所述第一接收终端。