公开(公告)号：US07034392B2

公开(公告)日：2006-04-25

申请号：US10886047

申请日：2004-07-08

申请人： Akio Hirakawa ,  Yoshiaki Fujita ,  Tomokazu Komazaki

发明人： Akio Hirakawa ,  Yoshiaki Fujita ,  Tomokazu Komazaki

IPC分类号： H01L23/053

CPC分类号： H01L25/165 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A filter chip lying on an upper surface of a top layer package substrate is connected to an upper surface ground electrode (235). The upper ground electrode (235) and a lower surface ground electrode (237) are connected to each other via through electrodes (261, 262, 263), ground wiring patterns (251, 252), first connecting lines (271 to 276), and second connecting lines (281, 282). The first connecting lines (271 to 276) are connected to the ground wiring patterns (251, 252), whereas the second connecting lines (281, 282) are not connected to the ground wiring patterns (251, 252), respectively. Owing to the provision of the connecting lines connected to the ground wiring patterns (251, 252) and the connecting lines unconnected to the ground wiring patterns (251, 252), the impedance between a multilayer package substrate and ground can be adjusted.

摘要翻译： 位于顶层封装衬底的上表面上的滤波器芯片连接到上表面接地电极（235）。 上接地电极（235）和下表面接地电极（237）经由电极（261,262,263），接地布线图案（251,252），第一连接线（271〜276）， 和第二连接线（281,282）。 第一连接线（271〜276）连接到接地布线图案（251,252），而第二连接线（281,282）分别不连接到接地布线图案（251,252）。 由于提供连接到接地布线图案（251,252）的连接线和未连接到接地布线图案（251,252）的连接线，可以调节多层封装基板和接地之间的阻抗。

公开(公告)号：US20050104203A1

公开(公告)日：2005-05-19

申请号：US10886047

申请日：2004-07-08

申请人： Akio Hirakawa ,  Yoshiaki Fujita ,  Tomokazu Komazaki

发明人： Akio Hirakawa ,  Yoshiaki Fujita ,  Tomokazu Komazaki

IPC分类号： H03H9/72 ,  H01L25/16 ,  H03H9/25 ,  H01L23/34

CPC分类号： H01L25/165 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A filter chip lying on an upper surface of a top layer package substrate is connected to an upper surface ground electrode (235). The upper ground electrode (235) and a lower surface ground electrode (237) are connected to each other via through electrodes (261, 262, 263), ground wiring patterns (251, 252), first connecting lines (271 to 276), and second connecting lines (281, 282). The first connecting lines (271 to 276) are connected to the ground wiring patterns (251, 252), whereas the second connecting lines (281, 282) are not connected to the ground wiring patterns (251, 252), respectively. Owing to the provision of the connecting lines connected to the ground wiring patterns (251, 252) and the connecting lines unconnected to the ground wiring patterns (251, 252), the impedance between a multilayer package substrate and ground can be adjusted.

摘要翻译： 位于顶层封装衬底的上表面上的滤波器芯片连接到上表面接地电极（235）。 上接地电极（235）和下表面接地电极（237）经由电极（261,262,263），接地布线图案（251,252），第一连接线（271〜276）， 和第二连接线（281,282）。 第一连接线（271〜276）连接到接地布线图案（251,252），而第二连接线（281,282）分别不连接到接地布线图案（251,252）。 由于提供连接到接地布线图案（251,252）的连接线和未连接到接地布线图案（251,252）的连接线，可以调节多层封装基板和接地之间的阻抗。

公开(公告)号：US6087194A

公开(公告)日：2000-07-11

申请号：US959855

申请日：1997-10-29

申请人： Hisao Matsukura ,  Yasuhiko Kudou ,  Hajime Hotta ,  Akio Hirakawa ,  Masaki Sugawara ,  Jiro Utsunomiya ,  Kiyoshi Kurosawa

发明人： Hisao Matsukura ,  Yasuhiko Kudou ,  Hajime Hotta ,  Akio Hirakawa ,  Masaki Sugawara ,  Jiro Utsunomiya ,  Kiyoshi Kurosawa

IPC分类号： H01L31/0203 ,  H01L33/38 ,  H01L33/62 ,  H01L21/00

CPC分类号： H01L33/62 ,  H01L31/0203 ,  H01L2224/16

摘要： Composite units of an optical semiconductor device and a supporting substrate are disclosed, in which the rear surface of the optical semiconductor device is provided with one or more electrode patterns and the top surface of the supporting substrate is provided with one or more electrode patterns. The optical semiconductor device and the supporting substrate are fixed to each other by once melting and solidifying one or more solder bumps which intervene between the one or more electrode patterns provided on the rear surface of the optical semiconductor device and the one or more electrode patterns provided on the top surface of the supporting substrate. A good grade of accuracy in the mutual geometric position of the optical semiconductor device and the supporting substrate is obtained in a horizontal direction due to a phenomenon called "the self alignment results" in this specification, in which a molten metal is inclined to become a ball based on surface tension. Methods for mounting an optical semiconductor device on a supporting substrate with a good grade of accuracy in the mutual geometric position therebetween in the horizontal direction, based on the same technical principle, are also disclosed. To realize the foregoing results, each of the composite units of an optical semiconductor device and supporting substrate in accordance with this invention is given various structures specific to each of them, and each of the methods in accordance with this invention is given various steps or processes specific to each of them.

摘要翻译： 公开了光半导体器件和支撑衬底的复合单元，其中光学半导体器件的后表面设置有一个或多个电极图案，并且支撑衬底的顶表面设置有一个或多个电极图案。 光学半导体器件和支撑衬底通过一次熔化和凝固一个或多个介于设置在光学半导体器件的后表面上的一个或多个电极图案和提供的一个或多个电极图案之间的焊料凸块彼此固定 在支撑基板的顶面上。 由于在本说明书中称为“自对准结果”的现象，在水平方向上获得了光半导体装置和支撑基板的相互几何位置的良好的精度等级，其中熔融金属倾向于变为 基于表面张力的球。 还公开了基于相同的技术原理将光学半导体器件在水平方向上在相互几何位置之间以相互几何位置准确地准确地安装在支撑基板上的方法。 为了实现上述结果，根据本发明的光学半导体器件和支撑衬底的复合单元中的每一个被给予各自特定的各种结构，并且根据本发明的每个方法被给予各种步骤或过程 具体到每个人。