公开(公告)号：US20020154463A1

公开(公告)日：2002-10-24

申请号：US10099600

申请日：2002-03-15

Inventor： Markus Paul Josef Mergens ,  Cornelius Christian Russ ,  John Armer ,  Koen Gerard Maria Verhaege

IPC: H02H009/00

CPC classification number: H01L27/0262 ,  H01L27/0251 ,  H01L29/866 ,  H03K17/0812 ,  H03K17/0814 ,  H03K17/305

Abstract: An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry. In one embodiment, the ESD protection circuit includes a pad, adapted for connection to a protected circuit node of the IC, and an ESD protection device, which is coupled between the pad and ground. A diode turn-on device is coupled in a forward conduction direction from the pad to a first gate of the ESD protection device. In a second embodiment, the ESD protection circuit is an SCR having an anode coupled to a first voltage supply line, and a cathode coupled to ground. A parasitic capacitance is coupled between each the voltage supply line and the grounded cathode.

Abstract translation: 具有保护电路的半导体集成电路（IC）中的静电放电（ESD）保护电路。 在一个实施例中，ESD保护电路包括适于连接到IC的受保护电路节点的焊盘和耦合在焊盘和接地之间的ESD保护装置。 二极管导通装置从正面传导方向耦合到ESD保护装置的第一栅极。 在第二实施例中，ESD保护电路是具有耦合到第一电压供应线的阳极和耦合到地的阴极的SCR。 寄生电容耦合在每个电源线和接地阴极之间。

公开(公告)号：US20010024353A1

公开(公告)日：2001-09-27

申请号：US09809907

申请日：2001-03-16

Inventor： Phillip A. Sanger ,  Lyon Mandelcorn ,  Leban E. Lesster ,  Frank A. Lindberg

IPC: H01G009/02

CPC classification number: H01G4/232 ,  H02M1/34 ,  H02M2001/346 ,  H03K17/0814 ,  H03K17/16 ,  Y02B70/1491

Abstract: A low-voltage, low-inductance device for storing electrical charge in a snubber circuit is disclosed as well as a method of minimizing inductance in the snubber circuit using the device. The device, a capacitor, comprises a plurality of extended electrodes, in parallel or series, that are joined to a positive conductor terminal at one end spray and at a negative conductor terminal at the other end spray so that end sprays of adjacent extended electrodes are alternately joined to the positive and negative conductor terminals. Accordingly, current flowing though adjacent extended electrodes is of substantially equal intensity but different in direction. As a result, inductance produced effectively cancels out that of adjacent extended electrodes. The method includes sandwiching an insulating film between the positive and negative conductor terminals and alternately joining the conductor terminals to the end sprays of extended electrodes so that current flows in opposite directions between end sprays of adjacent extended electrodes, thereby canceling out inductance.

Abstract translation: 公开了一种用于在缓冲电路中存储电荷的低电压，低电感装置以及使用该装置使缓冲电路中的电感最小化的方法。 该装置，电容器包括平行或串联的多个延伸电极，其在一端喷射处连接到正导体端子，在另一端喷射时与负导体端子连接，使得相邻延伸电极的末端喷射是 交替地连接到正负导体端子。 因此，流过相邻的延伸电极的电流具有基本相等的强度，但在方向上不同。 结果，产生的电感有效抵消了相邻的延伸电极的电感。 该方法包括在正和负导体端子之间夹着绝缘膜，并将导体端子交替地连接到延伸电极的末端喷雾，使得电流在相邻延​​伸电极的末端喷射之间沿相反方向流动，从而消除电感。

公开(公告)号：US06101107A

公开(公告)日：2000-08-08

申请号：US254980

申请日：1999-03-17

Applicant: Bengt Assow

Inventor： Bengt Assow

IPC: H02M1/34 ,  H02M3/335 ,  H03K17/0814

CPC classification number: H02M1/34 ,  H02M3/335 ,  H03K17/0814 ,  H02M2001/346 ,  Y02B70/1491

Abstract: The present invention relates to a snubber circuit, a voltage converter circuit as well as a method where the voltage converter circuit comprises a coupling element (DF), which can be influenced to conduct and not to conduct and across which the snubber circuit is connected, which comprises a first series circuit comprising a first capacitor (C1) and a first diode (D1) in parallel with at least one second series circuit comprising a second capacitor (C2) and at least one second diode (D2). All capacitors in the snubber circuit form a capacitive series circuit in parallel with the coupling element (DF), which has its beginning in the first capacitor (C1). The second capacitor (C2) is connected to the closest preceding capacitor in the capacitive series circuit via a third diode (D3), such that when a voltage is applied across the coupling element (DF) and this is influenced not to conduct, the capacitors (C1, C2) are charged in series, and when the coupling element thereafter is influenced to conduct, the capacitors are discharged in parallel and the coupling element does not start to conduct until the capacitors have been completely discharged.

Abstract translation: PCT No.PCT / SE97 / 01492 Sec。 371日期1999年3月17日 102（e）1999年3月17日PCT PCT 1997年9月8日PCT公布。 公开号WO98 / 12796 日期：1998年3月26日本发明涉及缓冲电路，电压转换器电路以及其中电压转换器电路包括耦合元件（DF）的方法，该耦合元件（DF）可以受到影响而不会导通 连接缓冲电路，其包括与包括第二电容器（C2）和至少一个第二二极管（D2）的至少一个第二串联电路并联的第一电容器（C1）和第一二极管（D1）的第一串联电路， 。 缓冲电路中的所有电容器形成与耦合元件（DF）并联的电容串联电路，耦合元件（DF）在第一电容器（C1）中起始。 第二电容器（C2）经由第三二极管（D3）连接到电容串联电路中最靠前的电容器，使得当耦合元件（DF）上施加电压并且不影响不导通时，电容器 （C1，C2）串联充电，当此后的耦合元件受到影响时，电容器并联放电，并且耦合元件不会开始导通，直到电容器完全放电。