Display panel and display device
    87.
    发明授权

    公开(公告)号:US11798487B2

    公开(公告)日:2023-10-24

    申请号:US17769457

    申请日:2021-03-01

    Abstract: A display panel has a display area including a plurality of pixel areas arranged in an array and a plurality of gate driving circuit areas. Each pixel area includes a pixel light-emitting sub-area and a pixel circuit sub-area arranged in a first direction. Pixel areas in each row correspond to at least two gate driving circuit areas each located between two adjacent pixel areas in this row. The display panel includes a gate driving circuit and a plurality of light-shielding portions. The gate driving circuit includes a plurality of shift registers that are cascaded. Each shift register includes a plurality of transistor groups, and each transistor group includes at least one transistor. Each light-shielding portion is located in a gate driving circuit area in which a transistor group is disposed, and is disposed on a periphery of the transistor group, and is electrically connected to a power supply signal line.

    Shift register unit set, gate driving circuit and display apparatus

    公开(公告)号:US11769455B2

    公开(公告)日:2023-09-26

    申请号:US17748788

    申请日:2022-05-19

    CPC classification number: G09G3/3266 G09G2310/0286

    Abstract: Disclosed is a shift register unit set, a gate driving circuit and a display apparatus, the shift register set including: cascaded n shift register units, and an ith stage of shift register unit in the shift register unit set includes: a first input sub-circuit and a second input sub-circuit, wherein the first input sub-circuit includes: a charging sub-circuit, a storing sub-circuit, an isolating sub-circuit, an output sub-circuit, a first electric leakage prevention sub-circuit configured to input an operation potential to the isolating sub-circuit under the control of the blanking pull-up control node, and a second electric leakage prevention sub-circuit configured to input the operation potential to a second electrode of the isolating transistor under the control of the first pull-up node, wherein there is an overlap among n composite output signals output by the n shift register units, n and i are positive integers, and 1≤i≤n.

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