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143 条记录 (耗时 0.027 秒)

    Reciprocating compressor and manufacturing method thereof
    81.
    发明申请
    Reciprocating compressor and manufacturing method thereof 审中-公开
    往复式压缩机及其制造方法

    公开(公告)号：US20060024181A1

    公开(公告)日：2006-02-02

    申请号：US11187971

    申请日：2005-07-25

    申请人： Dong-Han Kim

    发明人： Dong-Han Kim

    IPC分类号： F04B35/04 ,  F04B17/04

    CPC分类号： F04B35/045

    摘要： The present invention discloses a reciprocating compressor and a manufacturing method thereof. The reciprocating compressor includes a frame installed in a casing, an outer stator having a winding coil and being fixed to the frame, an inner stator disposed in the outer stator with a predetermined gap, and sintered by a powder metallurgy process using metal powder, a rotor having a permanent magnet between the outer stator and the inner stator, a cylinder disposed inside the inner stator of the reciprocating motor for forming a compression chamber, and sintered by a powder metallurgy process using metal powder, a piston slidably inserted into the inner circumference of the cylinder, for sucking and compressing gas by linear reciprocation, and a plurality of resonance springs for elastically supporting the connection part of the piston and the rotor, and inducing resonance of the piston. Accordingly, the cylinder is not deformed by the inner stator, and thus abrasion of the piston and the cylinder by deformation of the cylinder is prevented in advance. Moreover, the reciprocating compressor is easily manufactured by considerably simplifying the manufacturing process.

    摘要翻译： 本发明公开了一种往复式压缩机及其制造方法。 往复式压缩机包括安装在壳体中的框架，具有绕组线圈并固定到框架的外定子，具有预定间隙设置在外定子中的内定子，并且通过使用金属粉末的粉末冶金工艺进行烧结， 转子，其在外定子和内定子之间具有永磁体，设置在往复式电动机的内定子内部的用于形成压缩室的气缸，并通过使用金属粉末的粉末冶金工艺进行烧结，可滑动地插入内周的活塞 用于通过线性往复运动来吸入和压缩气体;以及多个共振弹簧，用于弹性地支撑活塞和转子的连接部分，并引起活塞的共振。 因此，缸体不会被内定子变形，从而预先防止活塞和气缸由于气缸的变形而发生的磨损。 此外，通过相当简化制造过程容易地制造往复式压缩机。

    Downlink signal configuring method and device in mobile communication system, and synchronization and cell searching method and device using the same
    82.
    再颁专利
    Downlink signal configuring method and device in mobile communication system, and synchronization and cell searching method and device using the same 有权

    公开(公告)号：USRE47278E1

    公开(公告)日：2019-03-05

    申请号：US13445263

    申请日：2012-04-12

    申请人： Kwang-Soon Kim ,  Jae-Young Ahn ,  Yong Soo Cho ,  Dong-Han Kim

    发明人： Kwang-Soon Kim ,  Jae-Young Ahn ,  Yong Soo Cho ,  Dong-Han Kim

    IPC分类号： H04J11/00 ,  H04L5/00 ,  H04L27/26

    摘要： Disclosed is a downlink signal configuring method and device, and synchronization and cell search method and device using the same in a mobile communication system. A downlink frame has plural symbols into which pilot subcarriers are distributively arranged with respect to time and frequency axes. Initial symbol synchronization and initial frequency synchronization are estimated by using a position at which autocorrelation of a cyclic prefix of a downlink signal and a valid symbol of the downlink is maximized, and cell search and integer-times frequency synchronization are estimated by using pilot subcarriers included in the estimated symbol. Fine symbol synchronization, fine frequency synchronization, and downlink frame synchronization is estimated by using an estimated cell search result. Downlink frequency and time tracking is performed, cell tracking is performed by using a position set of pilot subcarriers inserted into the downlink frame, fine symbol synchronization tracking and fine frequency synchronization tracking are repeated by using the pilot subcarriers to perform the frequency and time tracking of the downlink frame.

    Tape package
    84.
    发明授权
    Tape package 有权
    磁带包

    公开(公告)号：US08581373B2

    公开(公告)日：2013-11-12

    申请号：US13223624

    申请日：2011-09-01

    申请人： Dong-han Kim ,  So-young Lim

    发明人： Dong-han Kim ,  So-young Lim

    IPC分类号： H01L23/495 ,  H01L23/053

    CPC分类号： H01L23/4985 ,  H01L23/49838 ,  H01L24/06 ,  H01L2224/0603 ,  H01L2224/06155 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/351 ,  H01L2924/00

    摘要： A tape package providing a plurality of input and output portions each having a minimum pitch. The tape package includes a tape wiring substrate including first and second wirings, and a semiconductor chip mounted on the tape wiring substrate, and including a first edge, a first pad disposed adjacent to the first edge, and a second pad disposed to be farther spaced apart from the first edge than the first pad, where the first wiring is connected to a portion of the first pad that is spaced from the first edge by a first distance, and where the second wiring is connected to a portion of the second pad that is spaced from the first edge by a second distance that is greater than the first distance.

    摘要翻译： 一种提供多个具有最小间距的输入和输出部分的磁带封装。 所述带包装包括包括第一和第二布线的带布线基板，以及安装在所述带布线基板上的半导体芯片，并且包括第一边缘，邻近所述第一边缘设置的第一焊盘和设置成更远的间隔的第二焊盘 除了第一边缘之外，第一布线连接到第一焊盘的与第一边缘间隔开第一距离的部分，并且其中第二布线连接到第二焊盘的一部分， 与第一边缘间隔开大于第一距离的第二距离。

    Insert for carrier board of test handler
    85.
    发明授权
    Insert for carrier board of test handler 有权
    插入测试处理程序的承载板

    公开(公告)号：US08496113B2

    公开(公告)日：2013-07-30

    申请号：US12100729

    申请日：2008-04-10

    申请人： Yun-Sung Na ,  Tae-Hung Ku ,  Jae-Hyun Son ,  Dong-Han Kim ,  Young-Yong Kim

    发明人： Yun-Sung Na ,  Tae-Hung Ku ,  Jae-Hyun Son ,  Dong-Han Kim ,  Young-Yong Kim

    IPC分类号： B65D73/02

    CPC分类号： G01R31/2893

    摘要： An insert for a carrier board of a test handler is disclosed. In a first aspect, the latch block applying to the insert is detachably coupled to the insert body. The latch block can be reused, and thus this reduces wastage of resources and eliminates the insert replacement fee. In a second aspect, the insert pocket having hooks is detachably coupled to the insert body. The insert body can be reused. The latch unit is installed to the insert pocket, so that the damaged latch unit can be easily replaced. The insert forms a plurality of holes in the bottom of the loading part thereof, to expose the leads of the semiconductor devices through the holes downwardly. Thus, the insert can load semiconductor devices regardless of the dimensions of the semiconductor devices.

    摘要翻译： 公开了一种用于测试处理机的载板的插入件。 在第一方面，应用于插入件的闩锁块可拆卸地联接到插入体。 闩锁块可以重复使用，因此这减少了资源的浪费，并消除了插件更换费用。 在第二方面，具有钩的插入口可拆卸地联接到插入体。 插入体可以重复使用。 闩锁单元安装到刀片槽中，从而可以方便地更换损坏的闩锁单元。 插入件在其装载部分的底部形成多个孔，以通过孔向下暴露半导体器件的引线。 因此，无论半导体器件的尺寸如何，插入件可以加载半导体器件。

    Wiring substrate, tape package having the same, and display device having the same
    87.
    发明授权
    Wiring substrate, tape package having the same, and display device having the same 有权
    配线基板，具有该布线基板的带包装及其显示装置

    公开(公告)号：US08339561B2

    公开(公告)日：2012-12-25

    申请号：US12353317

    申请日：2009-01-14

    申请人： Ji-Hwan Hwang ,  Dong-Han Kim ,  Chul-Woo Kim ,  Chung-Ye Chung ,  Kwang-Jin Bae

    发明人： Ji-Hwan Hwang ,  Dong-Han Kim ,  Chul-Woo Kim ,  Chung-Ye Chung ,  Kwang-Jin Bae

    IPC分类号： G02F1/1345

    CPC分类号： H05K1/0277 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/50 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/111 ,  H05K1/189 ,  H05K2201/097 ,  H05K2201/09709 ,  H05K2201/10128 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00

    摘要： A wiring substrate includes a base film, a plurality of first wirings and a plurality of second wirings. The base film has a chip-mounting region configured for mounting a semiconductor chip thereon. The first wirings extend in a first direction from inside the chip-mounting region to outside the chip-mounting region, and include first connection end portions extending in a second direction different from the first direction. The first connection end portions may be formed inside the chip-mounting region and configured to electrically connect to the semiconductor chip. The second wirings extend in the first direction from inside the chip-mounting region to outside the chip-mounting region, and include second connection end portions extending in the opposite direction to the second direction in which the first connection end portions extend, and the second connection end portions may be formed inside the chip-mounting region and configured to electrically connect to the semiconductor chip.

    摘要翻译： 布线基板包括基膜，多个第一布线和多个第二布线。 基膜具有芯片安装区域，用于在其上安装半导体芯片。 第一布线沿芯片安装区域内的第一方向延伸到芯片安装区域的外部，并且包括沿与第一方向不同的第二方向延伸的第一连接端部。 第一连接端部可以形成在芯片安装区域的内部并且被配置为电连接到半导体芯片。 所述第二配线从所述芯片安装区域的内部朝向所述芯片安装区域的外侧沿所述第一方向延伸，并且包括沿与所述第一连接端部延伸的所述第二方向相反的方向延伸的第二连接端部， 连接端部可以形成在芯片安装区域内部，并且被配置为电连接到半导体芯片。

    Semiconductor package having test pads on top and bottom substrate surfaces and method of testing same
    89.
    发明授权
    Semiconductor package having test pads on top and bottom substrate surfaces and method of testing same 有权
    具有在顶部和底部衬底表面上的测试焊盘的半导体封装及其测试方法

    公开(公告)号：US08120024B2

    公开(公告)日：2012-02-21

    申请号：US11758176

    申请日：2007-06-05

    申请人： Eun-seok Song ,  Dong-han Kim ,  Hee-seok Lee

    发明人： Eun-seok Song ,  Dong-han Kim ,  Hee-seok Lee

    IPC分类号： H01L23/58

    CPC分类号： G01R31/2884 ,  H01L22/32 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

    摘要： A semiconductor package and testing method is disclosed. The package includes a substrate having top and bottom surfaces, a semiconductor chip mounted in a centrally located semiconductor chip mounting area of the substrate, and a plurality of test pads disposed on top and bottom surfaces of the substrate and comprising a first group of test pads configured on the top and bottom surfaces of the substrate and having a first height above the respective top and bottom surface of the substrate, and a second group of test pads disposed on the lower surface of the substrate and having a second height greater than the first, wherein each one of the second group of test pads includes a solder ball attached thereto.

    摘要翻译： 公开了半导体封装和测试方法。 封装包括具有顶表面和底表面的衬底，安装在衬底的位于中心的半导体芯片安装区域中的半导体芯片以及设置在衬底的顶表面和底表面上的多个测试焊盘，并且包括第一组测试焊盘 配置在衬底的顶表面和底表面上并且具有在衬底的相应顶部和底部表面上方的第一高度，以及设置在衬底的下表面上并具有大于第一衬底的第二高度的第二组测试焊盘 其中第二组测试垫中的每一个包括附接到其上的焊球。