公开(公告)号：US20110202804A1

公开(公告)日：2011-08-18

申请号：US13018002

申请日：2011-01-31

申请人： Stephen Kenneth Sunter

发明人： Stephen Kenneth Sunter

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/3177 ,  G01R31/318577

摘要： A circuit and method provide built-in measurement of delay changes in integrated circuit paths. The circuit includes a digital shift register to access multiple paths, and may be implemented in digital boundary scan to test I/O pin delays. Synchronous to a first frequency, the circuit applies an alternating signal to the paths and samples the paths' output logic values synchronous with a second frequency that is asynchronous and coherent to the first clock frequency. The shift register conveys the samples to a modulo counter that counts the number of samples between consecutive rising or consecutive falling edges in the signal samples from a selected path. Between the two edges, the path or a path characteristic is changed, and the resulting modulo count after the second edge is proportional to the change in delay. The circuit can compare the count, or the difference between counts, to test limits.

摘要翻译： 电路和方法提供集成电路路径中延迟变化的内置测量。 该电路包括一个数字移位寄存器来访问多个路径，并且可以在数字边界扫描中实现以测试I / O引脚延迟。 电路与第一频率同步，将交替信号施加到路径，并对与第一时钟频率异步和相干的第二频率同步的路径的输出逻辑值进行采样。 移位寄存器将样本传送到模计数器，其对来自所选路径的信号样本中的连续上升沿或连续下降沿之间的样本数进行计数。 在两个边缘之间，路径或路径特性被改变，并且在第二边缘之后产生的模数与延迟的变化成比例。 该电路可以将计数或计数之间的差值与测试极限进行比较。

公开(公告)号：US20110167311A1

公开(公告)日：2011-07-07

申请号：US12983016

申请日：2010-12-31

申请人： James Ray Bailey ,  Christopher W. Case ,  Michael Anthony Marra, III

发明人： James Ray Bailey ,  Christopher W. Case ,  Michael Anthony Marra, III

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/3177 ,  G06F11/2294

摘要： A system for testing or debugging a system including the integrated circuit having an embedded logic analyzer. In one embodiment, the system includes a computing device coupled to the logic analyzer for receiving the at least one output. A user interface run on the computing device assigns an attribute to at least one signal associated with the logic analyzer, determines a new signal or value not provided by the logic analyzer, the new signal or value being based upon the at least one signal as received from the logic analyzer and upon a predetermined definition, and presents the new signal or value to a system user.

摘要翻译： 一种用于测试或调试系统的系统，包括具有嵌入式逻辑分析仪的集成电路。 在一个实施例中，系统包括耦合到逻辑分析器的计算设备，用于接收至少一个输出。 在计算设备上运行的用户界面将属性分配给与逻辑分析器相关联的至少一个信号，确定未由逻辑分析器提供的新信号或值，新信号或值基于接收到的至少一个信号 从逻辑分析器和预定的定义，并将新的信号或值呈现给系统用户。

公开(公告)号：US20110161759A1

公开(公告)日：2011-06-30

申请号：US12648812

申请日：2009-12-29

申请人： Talal K. Jaber ,  David M. Wu

发明人： Talal K. Jaber ,  David M. Wu

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318575 ,  G01R31/318541

摘要： A scan architecture and design methodology yielding significant reduction in scan area and power overhead is generally presented. In this regard, an apparatus is introduced comprising a plurality of combinatorial logic clouds, scan cells coupled with the combinatorial logic clouds, the scan cells to load test vectors, wherein the scan cells comprise a plurality of first type scan cells and second type scan cells sequentially coupled with separate combinatorial logic cloud outputs, and a first scan clock and a second scan clock, wherein the first scan clock controls the first type scan cells and the second scan clock controls the second type scan cells. Other embodiments are also described and claimed.

摘要翻译： 通常会提供扫描结构和设计方法，显着减少扫描面积和功耗开销。 在这方面，引入了包括多个组合逻辑云，与组合逻辑云耦合的扫描单元，扫描单元以加载测试向量的装置，其中扫描单元包括多个第一类型扫描单元和第二类型扫描单元 与单独的组合逻辑云输出顺序耦合，以及第一扫描时钟和第二扫描时钟，其中第一扫描时钟控制第一类扫描单元，第二扫描时钟控制第二类扫描单元。 还描述和要求保护其他实施例。

公开(公告)号：US20110154140A1

公开(公告)日：2011-06-23

申请号：US13039517

申请日：2011-03-03

申请人： Lee D. Whetsel

发明人： Lee D. Whetsel

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318558 ,  G01R31/2851 ,  G01R31/3177 ,  G01R31/318536 ,  G01R31/318572 ,  G01R31/318594

摘要： The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.

摘要翻译： 本公开描述了用于直接访问存在于许多串行连接的JTAG Tap域的扫描路径中的JTAG Tap域的新颖的方法和装置。 由JTAG控制器直接扫描访问所选的Tap域，可以使用与Tap域关联并连接到JTAG控制器的辅助数字或模拟终端。 在直接扫描访问期间，辅助数字或模拟端子用作所选Tap域和JTAG控制器之间的串行数据输入和串行数据输出路径。

公开(公告)号：US20110145658A1

公开(公告)日：2011-06-16

申请号：US12967825

申请日：2010-12-14

申请人： Tsuyoshi Wasamoto ,  Toshiaki Watanabe

发明人： Tsuyoshi Wasamoto ,  Toshiaki Watanabe

IPC分类号： G06F11/25 ,  G06F12/00

CPC分类号： G06F21/79 ,  G06F2221/2101

摘要： An electronic apparatus is provided. A main control section outputs data including fiscal information input from an interface. A recording control section is connected to the main control section. The recording control section controls a recording section on the basis of the data output from the main control section to issue a receipt. A memory control section is connected to the main control section and a memory. The memory control section reads and writes the fiscal information from and to the memory under the control of the main control section. When the data is input to the main control section from the interface, the main control section controls the memory control section to write the fiscal data to the memory. A log creation section creates a log that the main control section controls the memory control section to read the fiscal information from the memory.

摘要翻译： 提供电子设备。 主控制部分输出包括从界面输入的财务信息的数据。 记录控制部分连接到主控制部分。 记录控制部分根据从主控部分输出的数据来发出收据来控制记录部分。 存储器控制部分连接到主控制部分和存储器。 存储器控制部分在主控制部分的控制下从存储器读取和写入财务信息。 当数据从接口输入到主控制部分时，主控制部分控制存储器控制部分将财务数据写入存储器。 日志创建部分创建一个日志，主控制部分控制内存控制部分从内存中读取财务信息。

公开(公告)号：US20110138240A1

公开(公告)日：2011-06-09

申请号：US13024666

申请日：2011-02-10

申请人： Ninh D. Ngo ,  Andy L. Lee ,  Kerry Veenstra

发明人： Ninh D. Ngo ,  Andy L. Lee ,  Kerry Veenstra

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： H03K19/17764 ,  G06F11/1004

摘要： Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

摘要翻译： 在可编程逻辑资源上提供错误检测电路。 可编程逻辑资源配置数据被加载到可以执行校验和计算的循环冗余校验（CRC）模块中。 在一个实施例中，校验和可以与预期值进行比较，期望值是在被编程到数据被编程到可编程逻辑资源之前或数据被编程到数据之前的预计算校验和。 在另一个实施例中，期望值可以包括在校验和计算中。 可以根据校验和和期望值之间的关系或校验和的值来生成指示是否检测到错误的输出。 该输出可以被发送到用户逻辑可访问的输出引脚。

公开(公告)号：US20110113298A1

公开(公告)日：2011-05-12

申请号：US12941837

申请日：2010-11-08

申请人： Petrus Marinus Cornelis Maria VAN DEN EIJNDEN

发明人： Petrus Marinus Cornelis Maria VAN DEN EIJNDEN

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/31855

摘要： A method of and an arrangement for testing connections on a printed circuit board between boundary-scan compliant circuit terminals of one or more boundary-scan compliant devices mounted at the printed circuit board and comprising a boundary-scan register of boundary-scan cells of the boundary-scan compliant circuit terminals. Under control of an electronic processing unit, boundary-scan properties of the or each boundary-scan compliant device are retrieved, a list comprising boundary-scan compliant circuit terminals is displayed, and a selection of at least a first and second boundary-scan compliant circuit terminal is received. Based on this selection, a boundary-scan cell of a first boundary-scan compliant circuit terminal of a boundary-scan compliant device is operated as a driver and a boundary-scan cell of a second boundary-scan compliant circuit terminal of a boundary-scan compliant device is operated as a sensor. The driver is controlled through data provided to the boundary-scan register. Data sensed by the sensor are latched in the boundary-scan register. The driver and sensor data are analyzed for a connection between the first and the second boundary-scan compliant circuit terminals and the result of the analyses is presented.

摘要翻译： 一种用于测试安装在印刷电路板上的一个或多个边界扫描兼容装置的边界扫描兼容电路端子之间的印刷电路板上的连接的方法和装置，并且包括边界扫描单元的边界扫描寄存器 符合边界扫描标准的电路端子。 在电子处理单元的控制下，检索符合或每个边界扫描的设备的边界扫描属性，显示包括符合边界扫描的电路终端的列表，并且选择至少第一和第二边界扫描兼容 电路端子被接收。 基于该选择，边界扫描兼容装置的第一边界扫描兼容电路端子的边界扫描单元作为驱动器和边界扫描兼容装置的第二边界扫描兼容电路端子的边界扫描单元被操作， 扫描兼容设备作为传感器工作。 通过提供给边界扫描寄存器的数据控制驱动程序。 传感器检测到的数据被锁存在边界扫描寄存器中。 分析驱动器和传感器数据以获得第一和第二边界扫描兼容电路端子之间的连接，并且呈现分析结果。

公开(公告)号：US20110113297A1

公开(公告)日：2011-05-12

申请号：US12614512

申请日：2009-11-09

申请人： David MACIOROWSKI ,  Christopher Shawn KROEGER

发明人： David MACIOROWSKI ,  Christopher Shawn KROEGER

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318533

摘要： Apparatus and other embodiments associated with a distributed Joint Test Access Group (JTAG) test bus controller (TBC) architecture are described. One example method includes providing first on-board scan programming (OSP) data to a first circuit board configured with a first TBC and located in a computer. The example method also includes providing second OSP data to a second circuit board configured with a second test bus controller and located in the same computer. The example method also includes controlling OSP to be performed at least partially in parallel on the first circuit board and the second circuit board.

摘要翻译： 描述了与分布式联合测试接入组（JTAG）测试总线控制器（TBC）架构相关联的装置和其他实施例。 一个示例性方法包括向配置有第一TBC并位于计算机中的第一电路板提供第一机载扫描编程（OSP）数据。 示例性方法还包括向配置有第二测试总线控制器并位于同一计算机中的第二电路板提供第二OSP数据。 该示例性方法还包括在第一电路板和第二电路板上至少部分并行地执行OSP的控制。

公开(公告)号：US20110113289A1

公开(公告)日：2011-05-12

申请号：US12869122

申请日：2010-08-26

申请人： Taro SHIBAGAKI ,  Satoru NUNOKAWA ,  Masaki KATO

发明人： Taro SHIBAGAKI ,  Satoru NUNOKAWA ,  Masaki KATO

IPC分类号： G06F11/25

CPC分类号： G06F11/0751

摘要： According to one embodiment, a malfunction predicting unit includes a level reduction unit, a first buffer gate unit, a second buffer gate unit, a comparator unit and a processing unit. The level reduction unit reduces an input digital signal to generate a level-reduced signal. The first buffer gate unit generates a first output signal. The first output signal has first or second level if the digital signal is or is not higher than a preset threshold level, respectively. The second buffer gate unit generates a second output signal. The second output signal has the first or second level if the level-reduced signal is or is not higher than the preset threshold level, respectively. The comparator unit compares the first and second output signals to generate a comparison result. The processing unit determines whether a malfunction will soon occur, based on the comparison result.

摘要翻译： 根据一个实施例，故障预测单元包括电平减小单元，第一缓冲器门单元，第二缓冲器门单元，比较器单元和处理单元。 电平降低单元减少输入数字信号以产生电平降低的信号。 第一缓冲门单元产生第一输出信号。 如果数字信号分别为或不高于预设阈值电平，则第一输出信号具有第一或第二电平。 第二缓冲门单元产生第二输出信号。 如果电平降低信号分别为或不高于预设阈值电平，则第二输出信号具有第一或第二电平。 比较器单元比较第一和第二输出信号以产生比较结果。 基于比较结果，处理单元确定是否将很快发生故障。

公开(公告)号：US20110107163A1

公开(公告)日：2011-05-05

申请号：US12985876

申请日：2011-01-06

申请人： Lee D. Whetsel

发明人： Lee D. Whetsel

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/3177 ,  G01R31/31722 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318541 ,  G01R31/318558

摘要： This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49, provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.