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公开(公告)号：US10152922B2
公开(公告)日：2018-12-11
申请号：US14863610
申请日：2015-08-10
Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. , WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
Inventor： Juncheng Xiao , Mang Zhao , Yong Tian
IPC: G09G3/3266 , G09G3/36 , G09G3/3233 , H01L21/822 , H01L27/12
Abstract: The present invention provides a scan driving circuit utilized to drive cascading scan lines. The scan driving circuit comprises a pull-down control module, a pull-down module, a reset control module, a reset module, a lower transmission module, a first bootstrap capacitor, a constant low voltage source, and a constant high voltage source. By use of the deployment of the reset module, the scan driving circuit of the present invention improves the stability of the scan driving circuit and meanwhile, the structure of the whole scan driving circuit is simplified.
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公开(公告)号：US20180336858A1
公开(公告)日：2018-11-22
申请号：US15326575
申请日：2016-12-29
Inventor： Mang Zhao
CPC classification number: G09G3/3677 , G09G2310/0286 , G09G2310/0291 , G09G2310/0294 , G09G2330/021 , H03K3/012 , H03K3/037
Abstract: Disclosed is a GOA driving circuit, which includes: an input control module, a latch module, a processing module, and a buffer module. A clock control signal is not used to control the input control module, so that the load for generating the clock control signal and power consumption of the circuit can be effectively reduced.
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公开(公告)号：US10115347B2
公开(公告)日：2018-10-30
申请号：US15112257
申请日：2016-06-23
Inventor： Mang Zhao
IPC: G09G3/32 , G09G3/3266 , G09G3/36
Abstract: The disclosure provides a scan driving circuit and a flat display device, the scan driving circuit includes a plurality of cascaded scan driving units, each of the scan driving units includes a forward/backward scanning circuit, applied to receive and process a superior level transmitted signal and a first inferior level transmitted signal, so as to control the scan driving circuit to scan forward and backward; an input circuit charges a pull-up control signal point and a pull-down control signal point according to the superior level transmitted signal and the first inferior level transmitted signal; a latch circuit latches the superior level transmitted signal and the first inferior level transmitted signal; a reset circuit clears and resets electric potential of the pull-up control signal point; a signal multiplexing circuit processes a same level transmitted signal, a second inferior level transmitted signal and latch data.
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公开(公告)号：US10089919B2
公开(公告)日：2018-10-02
申请号：US15316158
申请日：2016-11-16
Inventor： Mang Zhao
IPC: G09G3/20
Abstract: The present disclosure relates to a scanning driving circuit including a plurality of cascaded-connected scanning driving units. Each of the scanning driving unit includes a forward-backward scanning circuit, a first and a second input circuit outputting first and second input signals; a pull-down circuit outputting first or second pull-down signals and pulling down or charging a first pull-down control signal point or a second pull-down control signal point; a first and a second control circuit charging or pulling down the first pull-down control signal point or the second pull-down control signal point; and the first and the second output circuit generating the first and the second scanning driving signals for the first and the second scanning line to drive pixel cells.
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公开(公告)号：US10043474B2
公开(公告)日：2018-08-07
申请号：US14916343
申请日：2016-02-24
IPC: G09G3/36
Abstract: A gate driving circuit disposed on an array substrate and an LCD using the same are described. The gate driving circuit on the array substrate comprises a plurality of sequentially connected gate driving units. The gate driving circuit unit comprises an input module, a reset module, a latch module and a signal processing module. The signal processing module receives the current inverse stage-transmitting signal XQ(N), the low voltage signal, a second clock signal and a third clock signal to control on/off statuses of two transistors by the current stage-transmitting signal Q(N) so that the two transistors forms Nth gate signal G(N) and gate signal (N+1)th based on the second clock signal and the third clock signal. The present invention utilizes less clock signals and transistors, which is favorable to the narrower LCD's frame design and solves the problem of manufacturing process restriction of the LCD panel.
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Patent Agency Ranking
公开(公告)号：US09997124B2
公开(公告)日：2018-06-12
申请号：US15802886
申请日：2017-11-03
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Juncheng Xiao , Mang Zhao
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G2300/0408 , G09G2310/0251 , G09G2310/0283 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2330/04
Abstract: A GOA circuit and a liquid crystal device (LCD) are disclosed. The GOA circuit includes a plurality of GOA units and a control module. Each of the cascaded GOA units is configured for charging corresponding horizontal scanning lines within a display area when being driven by a first level clock, a second level clock, a first control clock, and a second control clock. After the horizontal scanning lines are fully charged by the GOA circuit, the control module is configured for resetting the gate driving signals to be at the first level, i.e., the invalid level, via the turn-on pulse signals and the negative-voltage constant-voltage source.
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公开(公告)号：US09966026B2
公开(公告)日：2018-05-08
申请号：US14905966
申请日：2015-12-23
Inventor： Mang Zhao
IPC: G09G3/36
CPC classification number: G09G3/3648 , G09G3/3677 , G09G2300/0408 , G09G2300/0439 , G09G2310/08
Abstract: A GOA substrate includes GOA circuit units connected in cascade. The GOA circuit unit includes an output module, a reset module, a latch module, and an input module. The output module is used for outputting the scan signal based on a trigger signal. The reset module is used for resetting the trigger signal based on the reset signal. The latch module is used to hold and pull down the electric potential of the trigger signal. The input module is used for receiving the scan signal outputted by the previous stage GOA circuit unit. The input module includes a first CMOS transmission gate and a first transistor. The input module can lower the equivalent on-resistance of the transistor, elevate the drive current between the input terminal and the output terminal, so to increase level transmission speed, lower drive power loss of the transistor and improve the stability of the circuit.
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公开(公告)号：US09947254B2
公开(公告)日：2018-04-17
申请号：US15238709
申请日：2016-08-16
Inventor： Shijuan Yi , Mang Zhao
IPC: G01R31/26 , G09G3/00 , G02F1/1345 , G09G3/36 , G02F1/1362
CPC classification number: G09G3/006 , G02F1/13452 , G02F1/13454 , G02F2001/136254 , G09G3/3648 , G09G2300/0426 , G09G2300/0819 , G09G2310/0297 , G09G2310/08 , G09G2330/12
Abstract: The present invention provides a liquid crystal display panel. The array test circuit (200) comprises a test control unit including a N type thin film transistor and a P type thin film transistor, wherein one thin film transistor is employed to be the output thin film transistor, and the other thin film transistor is employed to be the voltage stabilization thin film transistor. When the liquid crystal display panel is in the normal display state, the test control signal (ATEN) controls the output thin film transistor to be deactivated and controls the voltage stabilization thin film transistor to be activated so that the voltage difference of the gate and the source of the output thin film transistor is zero. Thus, the leakages on the data lines in the active display area (100) are consistent.
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公开(公告)号：US09934752B2
公开(公告)日：2018-04-03
申请号：US15238702
申请日：2016-08-16
IPC: G09G3/36
CPC classification number: G09G3/3688 , G09G3/20 , G09G3/3607 , G09G3/3648 , G09G2300/0426 , G09G2300/0452 , G09G2310/0275 , G09G2310/0289 , G09G2310/0291 , G09G2310/0297 , G09G2320/0219
Abstract: The present invention provides a demultiplex type display driving circuit, including: a plurality of drive units. Each drive unit comprises three demultiplex modules, and each demultiplex module includes two switch elements. The first switch element and the second switch element are controlled to be alternately on with the first branch control signal and the second branch control signal. The third branch control signal controls the two switch elements of the second and the third demultiplex modules to be alternately on to sequentially input the data signal to the first, the second, the third and the fourth data lines. Thus, division one to four of the data signal can be achieved with the three branch control signals. In comparison with prior art, the amount of the branch control signals is decreased, and meanwhile, the CMOS transmission gate is employed to be the switch element in the demultiplex modules.
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公开(公告)号：US09906222B2
公开(公告)日：2018-02-27
申请号：US15023380
申请日：2016-02-25
Inventor： Mang Zhao
IPC: G09G3/36 , H03K17/687
CPC classification number: H03K17/6872 , G09G3/3677 , G09G2310/0286
Abstract: A gate driving circuit and a liquid crystal display are disclosed. The gate driving circuit includes: an input and latch circuit, a signal processing circuit electrically connected with the input and latch circuit and an output buffering circuit electrically connected with the signal processing circuit. Wherein, the input and latch circuit or the signal processing circuit includes two switch modules which are disposed in parallel. Each switch module includes two switching tubes disposed in series, control terminals of the two switching tubes of one of the two switch modules are crosswise connected with control terminals of the two switching tubes of the other of the two switch modules. The present invention through disposing two switch modules and crosswise connecting the control terminals of the switching tubes, the stress degrees applied on the two switching transistors are the same so as to greatly increase the stability of the circuit operation.
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