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公开(公告)号：US20220344224A1
公开(公告)日：2022-10-27
申请号：US17435098
申请日：2020-02-27
Inventor： Yongqian LI , Can YUAN , Meng LI , Xuehuan FENG , Zhongyuan WU , Zhidong YUAN
Abstract: The present disclosure provides a motherboard and a manufacturing method for the motherboard, the motherboard includes at least one display area, a periphery area surrounding the at least one display area, a plurality of test terminals, an electrostatic discharge line, a plurality of resistors and at least one thin film transistor. The plurality of test terminals are respectively electrically connected to the electrostatic discharge line through the plurality of resistors. At least one of the plurality of resistors includes an inorganic nonmetal trace. The at least one thin film transistor includes an active layer, and the inorganic nonmetal trace includes a same semiconductor matrix material as the active layer of the at least one thin film transistor.
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公开(公告)号：US20220278182A1
公开(公告)日：2022-09-01
申请号：US17680790
申请日：2022-02-25
Inventor： Can YUAN , Yongqian LI , Zhidong YUAN
Abstract: The present disclose is related to an array substrate. The array substrate may include a base substrate; a driving transistor on the base substrate; an insulating layer on the driving transistor, the insulating layer comprising a via hole above a first electrode of the driving transistor; a conductive portion on the insulating layer; and a light emitting device on the conductive portion and electrically connected to the conductive portion. The conductive portion may be electrically connected to the first electrode of the driving transistor through the via hole. The light emitting device may be above the via hole, and an orthographic projection of the light emitting device on the base substrate may cover an orthographic projection of the via hole on the base substrate.
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公开(公告)号：US20210202679A1
公开(公告)日：2021-07-01
申请号：US16977928
申请日：2019-11-29
Inventor： Meng LI , Zhongyuan WU , Yongqian LI , Can YUAN , Zhidong YUAN , Xuehuan FENG , Lang LIU , Dacheng ZHANG
IPC: H01L27/32 , H01L51/52 , H01L51/56 , G09G3/3233
Abstract: A display substrate and a manufacturing method thereof and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. The sub-pixels are arranged in a sub-pixel array. At least one sub-pixel includes a first transistor, a second transistor, a third transistor and a storage capacitor. The first electrode of the third transistor is electrically connected to an active layer of the third transistor through a first via hole, and the first electrode of the third transistor is configured to be electrically connected to the light emitting element through a second via hole; the first via hole and the second via hole are at least partially overlapped with each other in a direction perpendicular to the base substrate.
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公开(公告)号：US20210202605A1
公开(公告)日：2021-07-01
申请号：US16977512
申请日：2019-11-29
Inventor： Zhongyuan WU , Yongqian LI , Can YUAN , Meng LI , Zhidong YUAN , Dacheng ZHANG , Lang LIU
IPC: H01L27/32
Abstract: A display substrate and a display device are provided. The display substrate includes sub-pixels which are arranged in a sub-pixel array in a first direction and a second direction. At least one sub-pixel includes a first transistor, a second transistor, a third transistor, and a storage capacitor. An active layer of the third transistor includes a body region and a first via hole region successively arranged in the first direction and electrically connected with each other; a first electrode of the third transistor is electrically connected to the first via hole region through a first via hole which is shifted in the second direction with respect to the body region, allowing the active layer incudes a first active layer side connecting the body region and the first via hole region; an extension direction of the first active layer side intersects with both the first direction and the second direction.
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公开(公告)号：US20210167162A1
公开(公告)日：2021-06-03
申请号：US17040260
申请日：2019-11-29
Inventor： Zhongyuan WU , Yongqian LI , Can YUAN , Meng LI , Zhidong YUAN , Xuehuan FENG , Lang LIU , Dacheng ZHANG
IPC: H01L27/32
Abstract: The present disclosure relates to the field of display technologies, and provides an array substrate, a manufacturing method thereof, and a display panel. In the array substrate, a substrate is provided with a first transistor and a second transistor, a first electrode of the first transistor is electrically connected to a gate of the second transistor; a conductive layer is disposed on the substrate, and includes a first conductor portion, a first semiconductor portion, a second conductor portion that are sequentially connected along a first direction; a first gate insulating layer is disposed on a side of the conductive layer away from the substrate; a first gate layer is disposed on a side of the first gate insulating layer away from the substrate to form the gate of the second transistor; a dielectric layer is disposed on the substrate to cover a part of the first conductor portion, a part of the second conductor portion and a part of the first gate layer, and an orthographic projection of a first via hole disposed on the dielectric layer on the substrate overlaps with orthographic projections of at least a part of the first conductor portion, at least a part of the second conductor portion and the first gate layer on the substrate; and a first source/drain layer is disposed on a side of the dielectric layer away from the substrate to cover the first via hole.
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Patent Agency Ranking
公开(公告)号：US20210134230A1
公开(公告)日：2021-05-06
申请号：US16639052
申请日：2019-07-18
Inventor： Zhidong YUAN , Can YUAN , Yongqian LI
IPC: G09G3/3275
Abstract: The present disclosure provides an organic light emitting diode (OLED) display device and control method thereof. The OLED display device includes: a plurality of subpixels that are arranged in an array having a plurality of rows and a plurality of columns, wherein at least one of the subpixels comprises a control transistor, a light emitting element, and a drive transistor for driving the light emitting element; a plurality of detection lines, wherein at least one of the detection lines is electrically connected with the control transistors of subpixels in a same column, for detecting an electrical property of the drive transistors of subpixels in the same column through respective control transistors; and a plurality of group detection control lines, wherein at least one of the group detection control lines is electrically connected with control transistors of a subpixel group, the subpixel group comprising subpixels in a first row and subpixels in a second row.
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公开(公告)号：US20250098448A1
公开(公告)日：2025-03-20
申请号：US18558269
申请日：2022-04-29
Inventor： Can YUAN , Yongqian LI , Dacheng ZHANG
IPC: H10K59/131 , G09G3/3233 , H10K59/124
Abstract: A display substrate, a method for operating the same, and a display device are provided. The display substrate includes a base substrate and a display unit. In the sub-pixel of the display substrate, the light emitting device includes a first electrode including a first portion and a second portion spaced apart from each other; the display unit further includes a connection structure and a first transfer electrode, the connection structure is electrically connected with the first portion of the first electrode and the second portion of the first electrode, and includes a connection portion located in the non-light-emitting region; the first transfer electrode is electrically connected with the first pole of the driving transistor and includes a portion located in the non-light-emitting region, and the connection portion is electrically connected with the portion of the first transfer electrode located in the non-light-emitting region.
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公开(公告)号：US20250095571A1
公开(公告)日：2025-03-20
申请号：US18555023
申请日：2023-01-12
Inventor： Zhidong YUAN , Can YUAN , Dacheng ZHANG , Yongqian LI
IPC: G09G3/3233
Abstract: A display substrate and a display device are disclosed, the display substrate has a plurality of display partitions arranged in a plurality of rows and columns, and at least one display partition includes a plurality of sub-pixels; the display substrate includes a base substrate and common scanning signal lines, the common scanning signal lines are provided on the base substrate, and include a plurality of first common scanning signal lines extending along a first direction and a plurality of second common scanning signal lines extending along a second direction, and the first direction is different from the second direction; each of the plurality of second common scanning signal lines is electrically connected to one first common scanning signal line, and is configured to provide a common scanning signal to one display partition.
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公开(公告)号：US20240404476A1
公开(公告)日：2024-12-05
申请号：US18261113
申请日：2022-05-24
Inventor： Zhidong YUAN , Yongqian LI , Can YUAN
IPC: G09G3/3266 , G09G3/3225
Abstract: A display substrate includes N groups of gate driving circuits and a multiplex circuit. Each group of gate driving circuits includes X gate driving circuits, and each gate driving circuit is electrically connected to rows of pixel circuits in a corresponding display zone. The X gate driving circuits are configured to output X scan signals of different functions to the rows of pixel circuits connected thereto. The multiplex circuit is electrically connected to N gate driving circuits of the N groups of gate driving circuits outputting scan signals of the same function, N selection control signal terminals and a start signal terminal. The multiplex circuit is configured to, under at least one selection control signal from at least one selection control signal terminal, select at least one group of gate driving circuits, and transmit a start signal from the start signal terminal to each selected group of gate driving circuits.
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公开(公告)号：US20240373687A1
公开(公告)日：2024-11-07
申请号：US18249359
申请日：2022-03-07
Inventor： Liu WU , Zhidong YUAN , Yongqian LI , Can YUAN
IPC: H10K59/131 , H10K59/10 , H10K59/121
Abstract: A profiled display panel, including a display area. The display area includes a plurality of display sub-areas; a plurality of cascade signal lines for coupling adjacent two of the gate driving sub-circuits. At least one cascade signal line includes a first cascade trace extending in a first direction and a second cascade trace extending in a second direction. The first cascade trace includes a plurality of first conductive patterns arranged on a first conductive layer and second conductive pattern arranged on a second conductive layer. The plurality of first conductive patterns are electrically connected to the second conductive pattern; and the second cascade trace includes a third conductive pattern arranged on the first conductive layer.
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