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公开(公告)号：US12248223B2
公开(公告)日：2025-03-11
申请号：US18760308
申请日：2024-07-01
Inventor： Xiaoxiao Chen , Yang Hu , Chuang Chen , Yuanhui Guo , Peng Jiang , Xia Shi , Yujie Gao , Ning Zhu , Yun Li , Jiantao Liu
IPC: G02F1/1362 , G02F1/1368
Abstract: An electrode structure, a display panel, an electronic device are provided, the electrode structure includes a first electrode portion, a second electrode portion and a conductive connection portion, the first electrode portion includes a first connection bar having a first side and a second side and a plurality of first electrode strips, ends of adjacent first electrode strips away from the first connection bar are open; the second electrode portion includes a second connection bar at a position of the first side away from the second side and a plurality of second electrode strips, the second connection bar includes a third side and a fourth side; the second electrode strips are connected with the second connection bar, ends of adjacent second electrode strips away from the second connection bar are open; ends of the conductive connection portion are connected with the first connection bar and the second connection bar.
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公开(公告)号：US12236912B2
公开(公告)日：2025-02-25
申请号：US17915712
申请日：2021-10-28
Inventor： Yanping Liao , Yingmeng Miao , Seungmin Lee , Xibin Shao , Shulin Yao , Yinlong Zhang , Qiujie Su , Cong Wang , Dongchuan Chen , Jiantao Liu
IPC: G09G3/36 , G09G3/3266 , G11C19/28
Abstract: A display panel, a driving method for the display panel and a display device. The display panel includes a gate driving circuit, the gate driving circuit includes shift registers of a plurality of stages arranged in sequence, the shift registers of the plurality of stages arranged in sequence are combined into N groups of gate driving sub-circuits, and shift registers in the N groups of gate driving sub-circuits are cascaded, respectively; an m-th group of gate driving sub-circuits in the N groups of gate driving sub-circuits comprises a shift register of an m-th stage and a shift register of an (m+L*N)th stage that are cascaded, where m is an integer that is greater than or equal to 1 and less than or equal to N, L is an integer that is greater than or equal to 1, N is an even number that is greater than or equal to 2.
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公开(公告)号：US12235551B2
公开(公告)日：2025-02-25
申请号：US17428622
申请日：2020-10-23
Inventor： Yihe Jia , Xiangqian Ding , Yongzhi Song , Xiaoxiang Zhang , Xiaolong Li , Lianjie Yang , Yan Pang , Jing Liu , Jiantao Liu
IPC: G02F1/1362 , G02F1/1343 , H01L27/12 , G02F1/1368
Abstract: The present disclosure provides an array substrate, a method for manufacturing the array substrate, and a display apparatus. The array substrate includes: a base substrate, a thin film transistor disposed on the base substrate; a first passivation layer, an organic film layer and a pixel electrode disposed on the thin film transistor; a connection structure for connecting the source electrode of the thin film transistor and the pixel electrode, wherein the connection structure is disposed in a via hole structure exposing the pixel electrode and the source electrode; or, the connection structure is disposed between the pixel electrode and the source electrode.
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公开(公告)号：US12218154B2
公开(公告)日：2025-02-04
申请号：US17401273
申请日：2021-08-12
Inventor： Xiaoyuan Wang , Yan Fang , Junhui Wu , Jiantao Liu
IPC: H01L27/12 , G02F1/1333 , G02F1/1337 , G02F1/1345 , G02F1/1362 , H01L23/00 , H01L23/544
Abstract: Provided are an array substrate and a display apparatus thereof. The array substrate includes a display region and a binding region located at a side of the display region; the binding region includes a first conductive layer disposed on the substrate and a planarization layer disposed at a side of the first conductive layer away from the substrate. The binding region includes a binding zone and a vacancy zone alternately disposed along an edge of the display region, the first conductive layer includes a plurality of binding pins disposed in the binding zone, and the planarization layer is provided with first openings exposing the plurality of binding pins and covering the binding zone and the vacancy zone.
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公开(公告)号：US12218149B2
公开(公告)日：2025-02-04
申请号：US17637893
申请日：2021-04-27
Inventor： Cong Wang , Yingmeng Miao , Dongchuan Chen , Seungmin Lee , Yanping Liao , Xibin Shao , Jiantao Liu
IPC: G02F1/1362 , G02F1/1333 , G02F1/1339 , G02F1/1343 , G02F1/1368 , H01L27/12
Abstract: A dual gate array substrate includes a plurality of groups of dual gate lines, a plurality of data lines, a plurality of pixel pairs and a plurality of common electrode lines, each common electrode line is arranged between two pixel units in a same pixel pair; and a layer where the common electrode line is located and a layer where a source/drain electrode of a thin film transistor is located are different layers and insulated from each other.
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Patent Agency Ranking
公开(公告)号：US12159878B2
公开(公告)日：2024-12-03
申请号：US17637485
申请日：2021-03-26
Inventor： Qiujie Su , Zhihua Sun , Tao Yang , Dongchuan Chen , Yingmeng Miao , Jiantao Liu , Seungmin Lee
IPC: G02F1/1343 , G02F1/1362 , G02F1/1368 , H01L27/12
Abstract: The present disclosure relates to an array substrate and a display device. The array substrate may include: a first substrate, and a plurality of pixel groups and a plurality of columns of data lines formed on the first substrate; wherein the plurality of pixel groups are arranged in an array along a row direction and a column direction, and each pixel group includes two sub-pixels arranged in the row direction; at least one sub-pixel of one of any two adjacent pixel groups in the row direction corresponds to the same color as one sub-pixel of the other pixel group; and any two adjacent sub-pixels in the row direction correspond to different colors; and each column of data line and each column of pixel groups are alternately arranged in the row direction.
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公开(公告)号：US12148401B2
公开(公告)日：2024-11-19
申请号：US17778865
申请日：2021-06-23
Inventor： Zhengri Lin , Wenchao Han , Xinle Wang , Yifan Song , Wanzhi Chen , Jing Liu , Wei Sun , Rui Liu , Xin Duan , Zhaohui Meng , Mingming Wang , Lianghao Zhang , Jiantao Liu
IPC: G09G3/36 , G02F1/133 , G02F1/1362 , H01L27/144
Abstract: A display substrate includes a base substrate, a plurality of photosensitive transistor units, a plurality of photosensitive ESD protection units, and at least one common signal line. The base substrate includes a display region, a peripheral region located at a periphery of the display region, and a binding region located at a side of the display region. The plurality of photosensitive transistor units, the plurality of photosensitive ESD protection units and the at least one common signal line are located in the peripheral region. The plurality of photosensitive transistor units is connected with binding pins in the binding region through a plurality of signal lines. At least one photosensitive ESD protection unit is connected with, and located between, at least one signal line and the common signal line.
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公开(公告)号：US11971640B2
公开(公告)日：2024-04-30
申请号：US17631334
申请日：2021-03-12
IPC: G02F1/1368 , G02F1/1362
CPC classification number: G02F1/1368 , G02F1/136254 , G02F1/136286
Abstract: The present disclosure provides a display substrate and a display device, and belongs to the field of display technology. The display substrate includes: a base substrate having a peripheral region, and thin film transistors disposed in the peripheral region of the base substrate. A gate electrode of the thin film transistor includes a plurality of sub-electrodes arranged at intervals.
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公开(公告)号：US11699409B2
公开(公告)日：2023-07-11
申请号：US17535967
申请日：2021-11-26
Inventor： Ming Deng , Jiantao Liu , Zhihua Sun , Wenliang Liu
IPC: G09G3/36 , G09G3/3225
CPC classification number: G09G3/3648 , G09G3/3225 , G09G2310/06 , G09G2310/08
Abstract: A display driving circuit is provided. The display driving circuit includes a source driver, a temperature detecting circuit, and a timing control circuit, wherein the temperature detecting circuit is connected to the timing control circuit, and is configured to detect a temperature of the source driver; and the timing control circuit is further connected to the source driver, and is configured to output a source signal to the source driver based on the temperature of the source driver; wherein a magnitude of a voltage of the source signal is negatively related to the temperature of the source driver.
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80.发明授权公开(公告)号：US11600220B2
公开(公告)日：2023-03-07
申请号：US17498411
申请日：2021-10-11
Inventor： Tianxun Xiu , Changcheng Liu , Yanping Liao , Yinlong Zhang , Ming Deng , Guohuo Su , Jiantao Liu
IPC: G09G3/32
Abstract: The disclosure discloses a timing controller board, a main control board, a display device and a detection method thereof. The timing controller board outputs a second level signal transmitted by a first fixed potential signal pin to the main control board through a detection circuit when a first data signal pin outputs a first level signal; the main control board loads a second potential signal transmitted by a second fixed potential signal pin to a second data signal pin and a clock signal pin through a switching circuit upon receiving the second level signal, to cause the main control board to stop sending a data signal to the timing controller board through the second data signal pin and stop sending a clock signal to the timing controller board through the clock signal pin.
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