公开(公告)号：US07633325B2

公开(公告)日：2009-12-15

申请号：US12075320

申请日：2008-03-11

申请人： Hyun-Seok Kim ,  Joon-Hyun Baek

发明人： Hyun-Seok Kim ,  Joon-Hyun Baek

IPC分类号： H03H11/16

CPC分类号： H03B27/00 ,  H03B2200/0078 ,  H03L7/0814

摘要： A signal generation apparatus includes a signal generation portion and a phase compensator. The phase compensator generates a phase error control signal that maintains a phase difference between the in-phase and quadrature-phase signals generated by the signal generation portion. The phase compensator includes an offset compensator and a delay compensator. The offset compensator is set to compensate for an offset voltage through the phase compensator. The delay compensator is set to compensate for a difference of delays through paths for the in-phase and quadrature-phase signals within the phase compensator.

摘要翻译： 信号发生装置包括信号产生部分和相位补偿器。 相位补偿器产生相位误差控制信号，其维持由信号产生部分产生的同相和正交相位信号之间的相位差。 相位补偿器包括偏移补偿器和延迟补偿器。 偏移补偿器被设置为补偿通过相位补偿器的偏移电压。 延迟补偿器被设置为补偿相位补偿器内的同相和正交相位信号的路径的延迟差。

公开(公告)号：US07622702B2

公开(公告)日：2009-11-24

申请号：US12129237

申请日：2008-05-29

申请人： Chung-Yu Wu ,  Po-Kang Lin ,  Li-Ju Lin ,  Wen-Chia Yang ,  Chen Wan

发明人： Chung-Yu Wu ,  Po-Kang Lin ,  Li-Ju Lin ,  Wen-Chia Yang ,  Chen Wan

IPC分类号： A61F2/14 ,  H03H11/16

CPC分类号： A61F9/08

摘要： The invention discloses a power controlling apparatus for a biochip including M regions. Each region includes a plurality of cells respectively. The power controlling apparatus includes a pulse generating module, a combinational circuit, and M controlling modules. The pulse generating module generates a pulse. The combinational circuit receives the pulse and generates M controlling signals. Each controlling signal has a predetermined phase which is different from the phase of the other controlling signal. The M controlling modules are electrically connected to the combinational circuit. Each of the M controlling signals corresponds to and activates one of the M controlling modules to selectively power on one corresponding region of the M regions. The cells in the corresponding region which is powered have an action potential refractory time that is longer than the power-on interval of the corresponding region.

摘要翻译： 本发明公开了一种用于包括M个区域的生物芯片的功率控制装置。 每个区域分别包括多个单元。 功率控制装置包括脉冲发生模块，组合电路和M个控制模块。 脉冲发生模块产生脉冲。 组合电路接收脉冲并产生M个控制信号。 每个控制信号具有与另一个控制信号的相位不同的预定相位。 M个控制模块电连接到组合电路。 M个控制信号中的每一个对应于并激活M个控制模块中的一个，以选择性地对M个区域的一个对应区域供电。 被供电的相应区域中的电池具有比对应区域的通电间隔更长的动作电位难度时间。

公开(公告)号：US20090284295A1

公开(公告)日：2009-11-19

申请号：US12465789

申请日：2009-05-14

申请人： Horst Diewald ,  Joerg Schreiner

发明人： Horst Diewald ,  Joerg Schreiner

IPC分类号： H03K23/00 ,  H03H11/16

CPC分类号： H03K5/1504 ,  H03K2005/00286 ,  H03M1/822

摘要： The present invention is an electronic device comprising a counter driven by an input clock signal for counting clock cycles and providing a count. A clock signal generating stage provides a first set of phase shifted clock signals having m different phases. The electronic device determines n least significant bits of the count of the counter from the logic states of the first set of m phase shifted clock signals.

摘要翻译： 本发明是一种电子设备，包括由用于计数时钟周期并提供计数的输入时钟信号驱动的计数器。 时钟信号发生级提供具有m个不同相位的第一组相移时钟信号。 电子设备根据第一组m个相移时钟信号的逻辑状态确定计数器计数的n个最低有效位。

公开(公告)号：US07579891B2

公开(公告)日：2009-08-25

申请号：US11745790

申请日：2007-05-08

申请人： Christian Ebner

发明人： Christian Ebner

IPC分类号： H03H11/16

CPC分类号： H04L7/0008 ,  H03B28/00 ,  H03F3/45085 ,  H03F3/45183 ,  H03F2203/45361 ,  H03F2203/45504 ,  H03F2203/45702

摘要： The invention relates to the generation of an electric output signal with a specified frequency and a phase (P) dependent upon a control signal (x) by means of weighted superposition of several input signals (s1, s2, s1*, s2*), which have the specified frequency but different input signals phases, whereby the weighted superposition is applied to a parallel switching of adjustable transconductance stages which are each adjusted by the control signal (x) and to each of which one of the input signals (s1, s2, s1*, s2*) is supplied. In order to be able to use this so-called phase interpolation to meet higher linearity requirements, the invention provides that for the generation of the output signal with a phase which lies between a first input signal phase (0°) of a first input signal (s1) and a second input signal phase (120°) of a second input signal (s2) which second phase is larger by a phase difference (120°), the first input signal (s1) and the second input signal (s2) and two further input signals (s1*1, s2*1 and S1*2, s2*2 resp.) are superimposed in a weighted fashion, whereby the two further input signals (s1*1, s2*1 and S1*2, s2*2 resp.) have phases different by the phase difference (120°) and are phase-shifted by one half (60°) of the phase difference with regard to the first and second input signals (s1, s2).

摘要翻译： 本发明涉及通过多个输入信号（s1，s2，s1 *，s2 *）的加权叠加产生具有指定频率的电输出信号和取决于控制信号（x）的相位（P） 其具有指定频率但不同的输入信号相位，由此将加权叠加应用于可调节跨导级的并行切换，每个跨导级均由控制信号（x）和输入信号（s1，s2）中的每一个调节 ，s1 *，s2 *）。 为了能够使用所谓的相位插值以满足更高的线性度要求，本发明提供了用于产生具有位于第一输入信号的第一输入信号相位（0°）之间的相位的输出信号 （s1）和第二相位大于相位差（120°）的第二输入信号（s2）的第二输入信号相位（120°），第一输入信号（s1）和第二输入信号（s2） 并且以加权方式叠加两个另外的输入信号（s1 * 1，s2 * 1和S1 * 2，s2 * 2），由此两个另外的输入信号（s1 * 1，s2 * 1和S1 * s2 * 2）具有相位相差（120°）的相位，并且相对于第一和第二输入信号（s1，s2）相移了相位差的一半（60°）。

公开(公告)号：US07576584B2

公开(公告)日：2009-08-18

申请号：US12002430

申请日：2007-12-14

申请人： Brad Porcher Jeffries ,  Bryan Scott Puckett

发明人： Brad Porcher Jeffries ,  Bryan Scott Puckett

IPC分类号： H03H11/16

CPC分类号： H03K3/356113 ,  H03K23/44

摘要： Clock generator embodiments are provided to generate half-rate I and Q clock signals. The generators are configured to insure fan-out limitations, to insure correct phasing at startup, to reduce the number of signal inverters in a critical path, and to reduce the total number of inverter structures to thereby substantially extend generator operational frequency. An exemplary generator embodiment requires only two tri-state inverters and four inverters. These clock generators are particularly suited for variety of electronic systems such as high speed data serializers.

摘要翻译： 提供时钟发生器实施例以产生半速率I和Q时钟信号。 发电机被配置为确保扇出限制，以确保启动时的正确定相，以减少关键路径中的信号反相器的数量，并且减少逆变器结构的总数，从而基本上延长发电机工作频率。 示例性发电机实施例仅需要两个三态反相器和四个反相器。 这些时钟发生器特别适用于各种电子系统，如高速数据串行器。

公开(公告)号：US20090140787A1

公开(公告)日：2009-06-04

申请号：US11791801

申请日：2007-02-01

申请人： Satoru Shiratsuchi ,  Kazuhiro Fujinuma ,  Kazuhiro Fujinuma ,  Kazuhiko Yamaguchi

发明人： Satoru Shiratsuchi ,  Kazuhiro Fujinuma ,  Kazuhiro Fujinuma ,  Kazuhiko Yamaguchi

IPC分类号： H03H11/16

CPC分类号： H04L27/0014 ,  H04L27/364 ,  H04L2027/0016 ,  H04L2027/0018 ,  H04L2027/0044 ,  H04L2027/0053 ,  H04L2027/0055 ,  H04L2027/0067

摘要： A quadrature modulator divides a first signal input as a local signal into an I channel signal and a Q channel signal orthogonal to each other and outputs a second signal having a desired phase delay corresponding to direct current voltages as for the first signal by giving the direct current voltages Vi and Vq to the I channel signal and the Q channel signal, respectively. A phase comparison unit detects a phase difference θ between the first signal and the second signal. A setting unit sets the desired phase delay. A controller section controls the direct current voltages supplied to the I channel signal and the Q channel signal respectively in the quadrature modulator so that an output value corresponding to the phase difference θ detected by the phase comparison unit is equal to a value corresponding to the desired phase delay set by the setting unit, and controls the direct current voltages to be the direct current voltages Vi and Vq satisfying the relation of Vi=cos θ and Vq=sin θ.

摘要翻译： 正交调制器将作为本地信号输入的第一信号划分成彼此正交的I信道信号和Q信道信号，并通过给出直接的方式输出具有与直流电压相对应的期望相位延迟的第二信号 电流电压Vi和Vq分别分配给I通道信号和Q通道信号。 相位比较单元检测第一信号和第二信号之间的相位差θ。 设置单元设置所需的相位延迟。 控制器部分控制正交调制器中分别提供给I通道信号和Q通道信号的直流电压，使得与由相位比较单元检测的相位差θ相对应的输出值等于对应于期望值的值 相位延迟，并且将直流电压控制为满足Vi =cosθ和Vq =sinθ的关系的直流电压Vi和Vq。

公开(公告)号：US20090027098A1

公开(公告)日：2009-01-29

申请号：US11880577

申请日：2007-07-23

申请人： Andy Nguyen

发明人： Andy Nguyen

IPC分类号： H03H11/16

CPC分类号： H03K5/1508

摘要： A phase shift circuit that includes two, rather than four, delay chains and corresponding selectors is described. This provides a significant area savings and reduces the intrinsic delay of the phase shift circuit, which is particularly beneficial for embodiments in which there is no intrinsic delay matching. In one specific implementation, the phase shift circuit includes a first delay circuit and a matching delay circuit. The first delay circuit provides a first delay that includes a first intrinsic delay and a first intentional delay. The delay matching circuit provides a matching delay that matches the first intrinsic delay. In one specific implementation, the phase shift circuit also includes a second delay circuit to provide a second delay that includes a second intrinsic delay and second intentional delay, where the second intrinsic delay matches the first intrinsic delay and the second intentional delay is half as long as the first intentional delay. Matching the intrinsic delay of the first delay circuit allows for comparing its output against a delayed version of the input signal, rather than the input signal. As a result, Fmax, the maximum frequency of the input signal at which the phase shift circuit may operate, is not limited by the intrinsic delay or by Fmin, the minimum frequency of the input signal at which the phase shift circuit may operate.

摘要翻译： 描述了包括两个而不是四个延迟链和对应的选择器的相移电路。 这提供了显着的面积节省并且减小了相移电路的固有延迟，这对于没有固有延迟匹配的实施例是特别有益的。 在一个具体实现中，相移电路包括第一延迟电路和匹配延迟电路。 第一延迟电路提供包括第一固有延迟和第一有意延迟的第一延迟。 延迟匹配电路提供与第一固有延迟匹配的匹配延迟。 在一个具体实现中，相移电路还包括第二延迟电路，以提供包括第二固有延迟和第二有意延迟的第二延迟，其中第二固有延迟与第一固有延迟匹配，并且第二有意延迟是一半长 作为第一个故意延误。 匹配第一延迟电路的固有延迟允许将其输出与输入信号的延迟版本进行比较，而不是输入信号。 结果，相移电路可以操作的输入信号的最大频率Fmax不受本征延迟或相移电路可以在其中操作的输入信号的最小频率Fmin的限制。

公开(公告)号：US20080265964A1

公开(公告)日：2008-10-30

申请号：US12107690

申请日：2008-04-22

申请人： Youn-Sik PARK

发明人： Youn-Sik PARK

IPC分类号： H03H11/16

CPC分类号： H03K19/018528 ,  H03K5/1515

摘要： In an example embodiments, a single signal-to-differential signal converter includes a first inverter for receiving and inverting a single input signal and outputting an inverted single input signal to a first node, and a first differential signal generating portion for generating a first signal and an inverted first signal which have the opposite phases to each other to second and third nodes in response to the single input signal. The single signal-to-differential signal converter further includes a second differential signal generating portion for generating a second signal and an inverted second signal which have the opposite phases to each other to the second and third nodes in response to the inverted single input signal, wherein the single signal-to-differential signal converter outputs differential signals such that the first and second signals applied to the second node are merged by a phase interpolation and the inverted first and second signals applied to the third node are merged by a phase interpolation.

摘要翻译： 在一个示例实施例中，单个信号至差分信号转换器包括第一逆变器，用于接收和反相单个输入信号并将反相的单个输入信号输出到第一节点;以及第一差分信号产生部分，用于产生第一信号 以及反向第一信号，其响应于单个输入信号而具有彼此相对于第二和第三节点的相位。 单个信号对差分信号转换器还包括第二差分信号产生部分，用于响应于反相的单个输入信号，产生具有相对于第二和第三节点的相反相位的第二信号和反相的第二信号， 其中单个信号对差分信号转换器输出差分信号，使得施加到第二个节点的第一和第二信号通过相位插值合并，并且施加到第三个节点的反相的第一和第二信号被相位插值合并。

公开(公告)号：US07443220B2

公开(公告)日：2008-10-28

申请号：US11602320

申请日：2006-11-21

申请人： Kazuhiro Tomita

发明人： Kazuhiro Tomita

IPC分类号： H03H11/16

CPC分类号： H03H7/21

摘要： A phase shift circuit includes a 45° phase corrector that performs vector synthesis of signals supposed to have a 45° phase difference, out of a plurality of sets of orthogonal phase signals having an about 45° phase difference and an equal amplitude, the orthogonal phase signals in each set having undergone 90° phase correction, and outputs signals resulting from the vector synthesis, whereby a phase error between the orthogonal phase signals in the different sets is eliminated by the vector synthesis to make it possible to correct their phase difference to accurately 45°.

摘要翻译： 相移电路包括：45°相位校正器，其在具有约45°相位差和相等振幅的多组正交相位信号中执行假设具有45°相位差的信号的矢量合成，正交相位 每个组中的信号经过90°相位校正，并且输出由矢量合成产生的信号，由此通过矢量合成消除了不同组中的正交相位信号之间的相位误差，使得可以将它们的相位差精确地校正 45°。

公开(公告)号：US20080111607A1

公开(公告)日：2008-05-15

申请号：US11558522

申请日：2006-11-10

申请人： Robert T. Hart

发明人： Robert T. Hart

IPC分类号： H03H11/16 ,  H03K3/00

CPC分类号： H03H7/461 ,  H01P1/18

摘要： A broad frequency range phase shift circuit is responsive to a radio-frequency signal generated by a radio-frequency source and generates a lagging phase signal and a leading phase signal, 90° out of phase with the lagging phase signal, corresponding to the radio-frequency signal. An operational amplifier has a signal input that receives the radio-frequency signal from the radio-frequency source and generates a low impedance amplified output signal. A series resonant circuit receives the amplified signal from the operational amplifier and shifts the phase of the amplified signal in an amount that approaches 90° as the amplified signal frequency approaches DC to 0° as the amplified signal frequency increases to the cut-off frequency. A transmission line receives the amplified signal from the operational amplifier and has an electrical length substantially equal to one-fourth of a wavelength corresponding to the cut-off frequency.

摘要翻译： 宽频率相移电路响应于由射频源产生的射频信号，并产生滞后相位信号和与滞后相位信号相差90°的超前相位信号，对应于无线电信号， 频率信号。 运算放大器具有从射频源接收射频信号的信号输入，并产生低阻抗放大输出信号。 当放大的信号频率增加到截止频率时，串联谐振电路接收来自运算放大器的放大信号并使放大的信号的相位以接近90°的量放大信号频率接近DC至0°。 传输线接收来自运算放大器的放大信号，其电长度基本上等于对应于截止频率的波长的四分之一。