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公开(公告)号：US20170162153A1
公开(公告)日：2017-06-08
申请号：US14786537
申请日：2015-10-12
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Mang Zhao
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/3696 , G09G2300/0408 , G09G2300/0871 , G09G2310/0286 , G09G2310/08
Abstract: The present invention provides a CMOS GOA circuit. The first NOR gate (Y1) and the second NOR gate (Y2) are located in the input control module (1). The two input ends of the first NOR gate (Y1) respectively receives the stage transfer signal (Q(N−1)) of the GOA unit circuit of the former stage and the global signal (Gas), and the two input ends of the second NOR gate (Y2) respectively receives the first clock signal (CK1) and the global signal (Gas). When the global signal (Gas) is high voltage level, the all the scan driving signals (G(N)) of the respective stages are controlled to be raised up to high voltage levels at the same time, and meanwhile, both the first NOR gate (Y1) and the second NOR gate (Y2) are controlled to output low voltage levels to control the inverted stage transfer signal (XQ(N)) to be high voltage level.
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公开(公告)号：US20170162152A1
公开(公告)日：2017-06-08
申请号：US14786167
申请日：2015-10-10
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Mang Zhao
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/3696 , G09G2300/0408 , G09G2300/0871 , G09G2310/0289 , G09G2310/0291 , G09G2310/08
Abstract: The present invention provides a CMOS GOA circuit. The latch module (3) comprises a NOR gate (Y), and the two input ends of the NOR gate (Y) are respectively inputted with the inverted stage transfer signal (XQ(N)) and the global signal (Gas). When the global signal (Gas) is high voltage level, all the scan driving signals (G(N)) of the respective stages are controlled to be raised up to high voltage levels at the same time, and meanwhile, the NOR gate (Y) is controlled to pull down voltage levels of the stage transfer signals (Q(N)) of the respective stages to clear and reset the stage transfer signals (Q(N)) of the respective stages. In comparison with prior art, an independent reset module is not required. The additional components, wirings, and reset signal are eliminated to reduce the rear of the GOA circuit, and simplify the complexity of the signal, which is beneficial to the design of narrow frame panel; besides, by locating the storage capacitors (7) to store the low voltage level of the stage transfer signal (Q(N)) as all the scan driving signals (G(N)) of the respective stages are raised up to high voltage levels at the same time to promote the stability of the GOA circuit.
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公开(公告)号：US09628050B2
公开(公告)日：2017-04-18
申请号：US14783100
申请日：2015-08-10
Inventor： Mang Zhao , Yong Tian , Gui Chen , Caiqin Chen , Xin Zhang
CPC classification number: H03K3/012 , G09G3/3677 , G09G2300/0408 , G09G2300/0814 , G09G2310/0202 , G09G2310/0289
Abstract: A scan driving circuit configured for driving cascaded scan lines is provided, which includes an input control module, a latch module, a driving-signal generation module, an output control module, a constant high voltage source and a constant low voltage source. The scan driving circuit of the present invention drives the input control module through cascade signals of a preceding stage and cascade signals of a succeeding stage, so as to reduce interference and the driving power consumption of the scan driving circuit.
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公开(公告)号：US10930192B2
公开(公告)日：2021-02-23
申请号：US16611237
申请日：2019-08-19
Inventor： Mang Zhao
IPC: G09G3/20
Abstract: A GOA circuit and a display panel. By using a first control clock and a third control clock in a forward and reverse scanning module to control a first node, the GOA circuit is able to avoid leakage of the first node during operation and improve the reliability of GOA circuit.
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公开(公告)号：US20200319519A1
公开(公告)日：2020-10-08
申请号：US16308815
申请日：2018-09-27
Inventor： Yuehua Yang , Mang Zhao
IPC: G02F1/1362
Abstract: Provided is a liquid crystal display panel adopting a notch design. The capacitance compensation module corresponding to the notch of the substrate and located in the peripheral area is disposed on the substrate. The capacitance compensation module includes semiconductor blocks and compensation traces. Each row of semiconductor blocks is correspondingly located below one first sub-scan line. Each compensation trace is correspondingly located above one column of semiconductor blocks and intersects with the first sub-scan lines. Each first sub-scan line is connected to one row of corresponding semiconductor blocks thereto via through holes. In any two first sub-scan lines, a capacitance between the first sub-scan line away from the notch, the corresponding semiconductor block and the compensation trace below the first sub-scan line is smaller than a capacitance between the first sub-scan line close to the notch, the corresponding semiconductor block and the compensation trace below the first sub-scan line.
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Patent Agency Ranking
公开(公告)号：US10789894B2
公开(公告)日：2020-09-29
申请号：US16332357
申请日：2018-12-21
Inventor： Lihua Zheng , Mang Zhao , Yong Tian
IPC: G09G3/3266 , G09G3/36
Abstract: A drive method for a display panel is provided. A first multiplex signal, a second multiplex signal, a third multiplex signal, a fourth multiplex signal, a fifth multiplex signal, and a sixth multiplex signal sequentially generate the high level pulse in the predetermined order in each of the first row periods of the (2i−1)th multiplex period. In addition, the first multiplex signal, the second multiplex signal, the third multiplex signal, the fourth multiplex signal, the fifth multiplex signal, and the sixth multiplex signal sequentially generate the high level pulse in a reverse order to the predetermined order in each of the second row periods of the (2i)th multiplex period. As a result, mura within the display picture of the display panel is eliminated to improve the display quality.
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公开(公告)号：US10714511B2
公开(公告)日：2020-07-14
申请号：US16336738
申请日：2018-09-12
Inventor： Mang Zhao
Abstract: A pull-down circuit of a gate driving unit includes: a first thin film transistor having a first gate to which a scan direction signal is inputted, a first source and a first drain to which a clock signal is inputted; a second thin film transistor having a second gate coupled to the first source, a second source coupled to a pull-down control node and a second drain to which a first direct-current voltage is inputted; a third thin film transistor having a third gate to which a first control signal is inputted, a third source coupled to the pull-down control node and a third drain coupled to a second direct-current voltage; and a fourth thin film transistor having a fourth gate coupled to the pull-down control node, a fourth source coupled to an output node and a fourth drain coupled to the second direct-current voltage.
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公开(公告)号：US10373578B2
公开(公告)日：2019-08-06
申请号：US15326575
申请日：2016-12-29
Inventor： Mang Zhao
Abstract: Disclosed is a GOA driving circuit, which includes: an input control module, a latch module, a processing module, and a buffer module. A clock control signal is not used to control the input control module, so that the load for generating the clock control signal and power consumption of the circuit can be effectively reduced.
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公开(公告)号：US10262618B2
公开(公告)日：2019-04-16
申请号：US15021461
申请日：2016-02-26
IPC: G09G3/36 , G02F1/13 , H03K17/687
Abstract: A GOA circuit includes GOA circuit units. Each GOA circuit has a holding module A first transistor and a second transistor in the holding module holds the voltage imposed on the first control node to be at high voltage level. Also, the transistors form a direct current passage between the first control node and a first fixed voltage at high voltage level so the voltage imposed on the first control node is not lowered due to electricity leakage. The GOA circuit unit can resolve the problem of easy leakage of electricity. When the scanning signals are output by the GOA circuit unit, the stability is highly ensured.
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公开(公告)号：US10216058B2
公开(公告)日：2019-02-26
申请号：US15326551
申请日：2017-01-07
IPC: G02F1/1368 , G02F1/1362 , H01L29/786 , G02F1/1343
Abstract: The present disclosure relates to a display panel including a first substrate, a second substrate, a liquid crystal layer between the first substrate and the second substrate, a masking layer on the first substrate, a buffering layer arranged on the masking layer and the first substrate, a first semiconductor layer on the buffering layer, and an active layer on the first semiconductor layer and the buffering layer. The present disclosure also relates to a display device. With such configuration, the leakage current of the TFTs may be reduced, which also reduces the cross-talk and the flicker of the liquid crystal panel.
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