公开(公告)号：US11856800B2

公开(公告)日：2023-12-26

申请号：US16806470

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsien-Wei Chen ,  Wen-Chih Chiou ,  Ming-Fa Chen ,  Sung-Feng Yeh

IPC: H10B99/00 ,  H01L27/146 ,  H01L21/56

CPC classification number: H10B99/00 ,  H01L27/14618 ,  H01L21/56

Abstract: A semiconductor device and method of manufacture are provided wherein the semiconductor device includes a first system on chip device bonded to a first memory device, a second system on chip device bonded to the first memory device, a first encapsulant surrounding the first system on chip device and the second system on chip device, a second encapsulant surrounding the first system on chip device, the second system on chip device, and the first memory device, and a through via extending from a first side of the second encapsulant to a second side of the first encapsulant, the through via being located outside of the first encapsulant.

公开(公告)号：US11848246B2

公开(公告)日：2023-12-19

申请号：US17314618

申请日：2021-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Sung-Feng Yeh

IPC: H01L23/36 ,  H01L27/06 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/36 ,  H01L21/56 ,  H01L23/31 ,  H01L25/0652 ,  H01L27/0688

Abstract: In an embodiment, a device includes: an interposer; a first integrated circuit device attached to the interposer; a second integrated circuit device attached to the interposer adjacent the first integrated circuit device; a heat dissipation die on the second integrated circuit device; and an encapsulant around the heat dissipation die, the second integrated circuit device, and the first integrated circuit device, a top surface of the encapsulant being coplanar with a top surface of the heat dissipation die and a top surface of the first integrated circuit device.

公开(公告)号：US20230343737A1

公开(公告)日：2023-10-26

申请号：US18346550

申请日：2023-07-03

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Ming-Fa Chen ,  Hsien-Wei Chen ,  Sung-Feng Yeh ,  Jie Chen

IPC: H01L25/00 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/80 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05124 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die and a plurality of bumps. The first semiconductor die has a front side and a backside opposite to each other. The second semiconductor die is disposed at the backside of the first semiconductor die and electrically connected to first semiconductor die. The plurality of bumps is disposed at the front side of the first semiconductor die and physically connects first die pads of the first semiconductor die. A total width of the first semiconductor die may be less than a total width of the second semiconductor die.

公开(公告)号：US11527465B2

公开(公告)日：2022-12-13

申请号：US17222088

申请日：2021-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Sung-Feng Yeh ,  Ming-Fa Chen ,  Hsien-Wei Chen

IPC: H01L23/498 ,  H01L25/10 ,  H01L25/00 ,  H01L21/683 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, forming stacked vias in the plurality of dielectric layers with the stacked vias forming a continuous electrical connection penetrating through the plurality of dielectric layers, forming a dielectric layer over the stacked vias and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding.

公开(公告)号：US20220367466A1

公开(公告)日：2022-11-17

申请号：US17870296

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsien-Wei Chen ,  Wen-Chih Chiou ,  Ming-Fa Chen ,  Sung-Feng Yeh

IPC: H01L27/105 ,  H01L27/146

Abstract: A semiconductor device and method of manufacture are provided wherein the semiconductor device includes a first system on chip device bonded to a first memory device, a second system on chip device bonded to the first memory device, a first encapsulant surrounding the first system on chip device and the second system on chip device, a second encapsulant surrounding the first system on chip device, the second system on chip device, and the first memory device, and a through via extending from a first side of the second encapsulant to a second side of the first encapsulant, the through via being located outside of the first encapsulant.

公开(公告)号：US20220310470A1

公开(公告)日：2022-09-29

申请号：US17314618

申请日：2021-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Sung-Feng Yeh

IPC: H01L23/36 ,  H01L27/06 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56

Abstract: In an embodiment, a device includes: an interposer; a first integrated circuit device attached to the interposer; a second integrated circuit device attached to the interposer adjacent the first integrated circuit device; a heat dissipation die on the second integrated circuit device; and an encapsulant around the heat dissipation die, the second integrated circuit device, and the first integrated circuit device, a top surface of the encapsulant being coplanar with a top surface of the heat dissipation die and a top surface of the first integrated circuit device.

公开(公告)号：US20220301973A1

公开(公告)日：2022-09-22

申请号：US17838648

申请日：2022-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Sung-Feng Yeh ,  Ming-Fa Chen

IPC: H01L23/367 ,  H01L23/373 ,  H01L25/065 ,  H01L25/18 ,  H01L21/683 ,  H01L23/538

Abstract: A package structure and method of manufacturing is provided, whereby heat dissipating features are provided for heat dissipation. Heat dissipating features include conductive vias formed in a die stack, thermal chips, and thermal metal bulk, which can be bonded to a wafer level device. Hybrid bonding including chip to chip, chip to wafer, and wafer to wafer provides thermal conductivity without having to traverse a bonding material, such as a eutectic material. Plasma dicing the package structure can provide a smooth sidewall profile for interfacing with a thermal interface material.

公开(公告)号：US11342297B2

公开(公告)日：2022-05-24

申请号：US16877512

申请日：2020-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Hsien-Wei Chen ,  Jie Chen ,  Sen-Bor Jan ,  Sung-Feng Yeh

IPC: H01L23/544 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: A package structure including at least one die laterally encapsulate by an encapsulant, a bonding film and an interconnect structure is provided. The bonding film is located on a first side of the encapsulant, and the bonding film includes a first alignment mark structure. The package structure further includes a semiconductor material block located on the bonding film. The interconnect structure is located on a second side of the encapsulant opposite to the first side, and the interconnect structure includes a second alignment mark structure. A location of the first alignment mark structure vertically aligns with a location of the second alignment mark structure.

公开(公告)号：US11335656B2

公开(公告)日：2022-05-17

申请号：US17027175

申请日：2020-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chia Hu ,  Ching-Pin Yuan ,  Sung-Feng Yeh ,  Sen-Bor Jan ,  Ming-Fa Chen

IPC: H01L23/00 ,  H01L23/544 ,  H01L25/065 ,  H01L23/522

Abstract: A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads.

公开(公告)号：US11264343B2

公开(公告)日：2022-03-01

申请号：US16929708

申请日：2020-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Sung-Feng Yeh ,  Hsien-Wei Chen ,  Jie Chen

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/538

Abstract: A package includes a first die that includes a first metallization layer, one or more first bond pad vias on the first metallization layer, wherein a first barrier layer extends across the first metallization layer between each first bond pad via and the first metallization layer, and one or more first bond pads on the one or more first bond pad vias, wherein a second barrier layer extends across each first bond pad via between a first bond pad and the first bond pad via, and a second die including one or more second bond pads, wherein a second bond pad is bonded to a first bond pad of the first die.