PROTOCOL-FRAMED CLOCK LINE DRIVING FOR DEVICE COMMUNICATION OVER MASTER-ORIGINATED CLOCK LINE

    公开(公告)号:US20190171611A1

    公开(公告)日:2019-06-06

    申请号:US16162524

    申请日:2018-10-17

    Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. A method for transmitting data over a serial bus includes receiving from a first line of the serial bus a clock signal used for timing transmission of data on a second line of the serial bus, activating a driver after the first line has transitioned from a first signaling state to a second signaling state while the data is being transmitted on the second line, driving the first line to the first signaling state to transmit a first bit of data when the first bit of data has a first value, and refraining from driving the first line to the first signaling state to transmit a first bit of data when the first bit of data has a second value.

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