Bias circuit for use with divided bit lines

    公开(公告)号:US10819936B2

    公开(公告)日:2020-10-27

    申请号:US16275092

    申请日:2019-02-13

    Abstract: An image sensor includes a pixel array including a plurality of pixels. Each pixel is coupled to generate image data in response to incident light. A bit line is coupled to a column of pixels of the pixel array and is separated into first and second portions. Each portion is coupled to a corresponding portion of rows of pixels of the pixel array. A readout circuit coupled to the bit line to read out the image data from the pixel array. The readout circuit includes a cascode device coupled between the first and second portions of the bit line. The cascode device is coupled to be biased to electrically separate the first and second portions of the bit line from one another such that a capacitance of each portion of the bit line does not affect a settling time of an other portion of the bit line.

    Bitline settling improvement and FPN reduction by floating bitline during charge transfer

    公开(公告)号:US10290673B1

    公开(公告)日:2019-05-14

    申请号:US15853463

    申请日:2017-12-22

    Abstract: A photodiode is adapted to accumulate image charges in response to incident light. A transfer transistor is coupled between the photodiode and a floating diffusion to transfer the image charges from the photodiode to the floating diffusion. A transfer gate voltage controls the transmission of the image charges from a transfer receiving terminal of the transfer transistor to the floating diffusion. A reset transistor is coupled to supply a supply voltage to the floating diffusion. A source follower transistor is coupled to receive voltage of the floating diffusion from a gate terminal of the source follower and provide an amplified signal to a source terminal of the source follower. A row select transistor is coupled to enable the amplified signal from the SF source terminal and output the amplified signal to a bitline. A bitline enable transistor is coupled to link between the bitline and a bitline source node. The bitline source node is coupled to a blacksun voltage generator. A current source generator is coupled between the bitline source node and a ground. The current source generator provides adjustable current to the bitline source node through a bias transistor controlled by a bias control voltage.

    Bitline settling improvement by using dummy pixels for clamp

    公开(公告)号:US10165210B1

    公开(公告)日:2018-12-25

    申请号:US15909267

    申请日:2018-03-01

    Abstract: A photodiode is adapted to accumulate image charges in response to incident light. A transfer transistor is coupled between the photodiode and a floating diffusion to transfer the image charges accumulated in the photodiode to the floating diffusion. A reset transistor is coupled to supply a supply voltage to the floating diffusion. A source follower transistor is coupled to receive voltage of the floating diffusion from a SF gate terminal and provide an amplified signal to a source follower source terminal. A row select transistor is coupled to receive the amplified signal from the SF source terminal and output the amplified signal to a bitline. A bitline enable transistor controlled by a bitline enable voltage is coupled to link between the bitline and a bitline source node. The bitline is coupled to an idle voltage generator, a blacksun voltage generator, and a clamp voltage generator. These three voltage generators are each constructed out of a plurality of modified dummy pixels based on the dummy pixels in the dummy rows of an image sensor pixel array.

    High dynamic range image sensor read out architecture using in-frame multi-bit exposure control

    公开(公告)号:US09955091B1

    公开(公告)日:2018-04-24

    申请号:US15384859

    申请日:2016-12-20

    Inventor: Tiejun Dai Rui Wang

    Abstract: A pixel circuit includes a photodiode to accumulate image charge in response to incident light. A transfer transistor is disposed between the photodiode and a floating diffusion disposed in the first semiconductor layer to selectively transfer the image charge accumulated in the photodiode to the floating diffusion. A select circuit is disposed in second semiconductor layer coupled to a control terminal of the transfer transistor through a hybrid bond between the first and second semiconductor layers to select between first and second transfer control signals to control the transfer transistor. The select circuit is coupled to output the first transfer control signal in response to a precharge enable signal during a read out operation of a different row, and output the second transfer control signal in response to a sample enable signal during a read out operation of the row.

    Row decoder for high dynamic range image sensor using in-frame multi-bit exposure control

    公开(公告)号:US09888185B1

    公开(公告)日:2018-02-06

    申请号:US15384866

    申请日:2016-12-20

    Inventor: Rui Wang Tiejun Dai

    Abstract: A pixel circuit includes a transfer transistor coupled between a photodiode and a floating diffusion to transfer image charge to the floating diffusion. A precharge offset signal is representative of a difference between a row that includes the transfer transistor and a different row that is being read out. The selection circuit is coupled to select between first and second transfer control signals to control the transfer transistor. The selection circuit is coupled to output the first transfer control signal in response to a precharge enable signal during a read out operation of the different row. The precharge enable signal is generated in response to a comparison of a precharge offset signal and an exposure value signal. The selection circuit is coupled to output the second transfer control signal in response to a sample enable signal during a read out operation of the row that includes the transfer transistor.

    Feedback capacitor formed by bonding-via in pixel level bond

    公开(公告)号:US09859312B1

    公开(公告)日:2018-01-02

    申请号:US15427928

    申请日:2017-02-08

    Abstract: An image sensor includes a photodiode disposed in a first semiconductor material, and the photodiode is positioned to absorb image light through the backside of the first semiconductor material. A first floating diffusion is disposed proximate to the photodiode and coupled to receive image charge from the photodiode in response to a transfer signal applied to a transfer gate disposed between the photodiode and the first floating diffusion. A second semiconductor material, including a second floating diffusion, is disposed proximate to the frontside of the first semiconductor material. A dielectric material is disposed between the first semiconductor material and the second semiconductor material, and includes a first bonding via extending from the first floating diffusion to the second floating diffusion, a second bonding via disposed laterally proximate to the first bonding via, and a third bonding via disposed laterally proximate to the first bonding via.

    Calibration circuitry and method for a time of flight imaging system

    公开(公告)号:US09720076B2

    公开(公告)日:2017-08-01

    申请号:US14473803

    申请日:2014-08-29

    CPC classification number: G01S7/497 G01S7/483 G01S17/89 G06F3/017

    Abstract: A time of flight imaging system includes a light source coupled to emit light pulses to an object in response a light source modulation signal generated in response to a reference modulation signal. Each pixel cell of a time of flight pixel cell array is coupled to sense light pulses reflected from the object in response a pixel modulation signal. A programmable pixel delay line circuit is coupled to generate the pixel modulation signal with a variable pixel delay programmed in response to a pixel programming signal. A control circuit is coupled to receive pixel information from the time of flight pixel array representative of the sensed reflected light pulses. The control circuit is coupled to vary the pixel programming signal during a calibration mode to synchronize the light pulses emitted from the light source with the pulses of the pixel modulation signal.

    READOUT CIRCUITRY TO MITIGATE COLUMN FIXED PATTERN NOISE OF AN IMAGE SENSOR
    68.
    发明申请
    READOUT CIRCUITRY TO MITIGATE COLUMN FIXED PATTERN NOISE OF AN IMAGE SENSOR 有权
    读取电路减小图像传感器的柱固定图形噪声

    公开(公告)号:US20170054931A1

    公开(公告)日:2017-02-23

    申请号:US14828404

    申请日:2015-08-17

    CPC classification number: H04N5/378 H04N5/365

    Abstract: Techniques and mechanisms to mitigate fixed pattern noise in image sensor data. In an embodiment, readout circuitry includes an adaptive analog-to-digital converter (ADC) comprising a differential amplifier and a feedback path coupled across the differential amplifier, where the ADC is to receive a ramp signal, a control signal associated with a transition rate of the ramp signal, and an analog signal generated by one or more pixels. In another embodiment, the feedback path and/or one or more other circuit elements coupled to the differential amplifier are configured, based on the control signal, to provide one of multiple loop gains with the differential amplifier. The ADC provides a digital output to determine a comparison based on the ramp signal and the analog signal.

    Abstract translation: 降低图像传感器数据中固定模式噪声的技术和机制。 在一个实施例中,读出电路包括自适应模数转换器(ADC),该自适应模数转换器(ADC)包括差分放大器和耦合在差分放大器两端的反馈路径,其中ADC将接收斜坡信号,与转换速率相关的控制信号 的斜坡信号,以及由一个或多个像素产生的模拟信号。 在另一个实施例中,耦合到差分放大器的反馈路径和/或一个或多个其他电路元件基于控制信号被配置为提供差分放大器的多个环路增益之一。 ADC提供数字输出,以确定基于斜坡信号和模拟信号的比较。

    STACKED EMBEDDED SPAD IMAGE SENSOR FOR ATTACHED 3D INFORMATION
    69.
    发明申请
    STACKED EMBEDDED SPAD IMAGE SENSOR FOR ATTACHED 3D INFORMATION 有权
    嵌入式嵌入式图像传感器,用于附加的3D信息

    公开(公告)号:US20160240579A1

    公开(公告)日:2016-08-18

    申请号:US14624198

    申请日:2015-02-17

    Abstract: A pixel array includes a plurality of visible light pixels arranged in the pixel array. Each one of the plurality of visible light pixels includes a photosensitive element arranged in a first semiconductor die to detect visible light. Each one of the plurality of visible light pixels is coupled to provide color image data to visible light readout circuitry disposed in a second semiconductor die stacked with and coupled to the first semiconductor die in a stacked chip scheme. A plurality of infrared (IR) pixels arranged in the pixel array. Each one of the plurality of IR pixels includes a single photon avalanche photodiode (SPAD) arranged in the first semiconductor die to detect IR light. Each one of the plurality of visible light pixels is coupled to provide IR image data to IR light readout circuitry disposed in the second semiconductor die.

    Abstract translation: 像素阵列包括排列在像素阵列中的多个可见光像素。 多个可见光像素中的每一个包括布置在第一半导体管芯中以检测可见光的感光元件。 多个可见光像素中的每一个被耦合以向布置在第二半导体管芯中的可见光读出电路提供彩色图像数据,所述可见光读出电路以叠层芯片方案堆叠并耦合到第一半导体管芯。 布置在像素阵列中的多个红外(IR)像素。 多个IR像素中的每一个包括布置在第一半导体管芯中以检测IR光的单个光子雪崩光电二极管(SPAD)。 多个可见光像素中的每一个被耦合以向设置在第二半导体管芯中的IR光读出电路提供IR图像数据。

    Feed-forward technique for power supply rejection ratio improvement of bit line
    70.
    发明授权
    Feed-forward technique for power supply rejection ratio improvement of bit line 有权
    前馈技术的电源抑制比提高了位线

    公开(公告)号:US09148596B1

    公开(公告)日:2015-09-29

    申请号:US14247855

    申请日:2014-04-08

    CPC classification number: H04N5/3698 H04N5/357 H04N5/378

    Abstract: An image sensor read out circuit includes a first current mirror circuit in which a second current conducted through a second current path is controlled in response to a first current conducted through the first current path. The second current is conducted through an amplifier transistor of a pixel circuit. A first current source is coupled to the first current path to provide a substantially constant current component of the first current. A second current source is coupled to a power supply rail of the pixel circuit and coupled to the first current path to provide a ripple current component of the first current. The ripple current component provided by the second current source is responsive to a ripple in the power supply rail. The first current is responsive to a sum of the currents from the first and second current sources.

    Abstract translation: 图像传感器读出电路包括第一电流镜电路,其中响应于通过第一电流路径传导的第一电流来控制通过第二电流路径传导的第二电流。 第二电流通过像素电路的放大器晶体管导通。 第一电流源耦合到第一电流路径以提供第一电流的基本上恒定的电流分量。 第二电流源耦合到像素电路的电源轨,并耦合到第一电流路径以提供第一电流的纹波电流分量。 由第二电流源提供的纹波电流分量响应于电源轨道中的纹波。 第一电流响应于来自第一和第二电流源的电流的总和。

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