公开(公告)号：US10778653B2

公开(公告)日：2020-09-15

申请号：US16287973

申请日：2019-02-27

Applicant: Amazon Technologies, Inc.

Inventor： Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Christopher Joseph Pettey ,  Nafea Bshara ,  Asif Khan ,  Mark Bradley Davis ,  Prateek Tandon

IPC: H04L29/06 ,  G06F9/50 ,  H04L9/32 ,  G06F15/78

Abstract: The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include encrypting the configuration data to generate encrypted configuration data. The method can include signing the encrypted configuration data using a private key. The method can include transmitting the signed encrypted configuration data in response to the request.

公开(公告)号：US10746792B1

公开(公告)日：2020-08-18

申请号：US16206761

申请日：2018-11-30

Applicant: Amazon Technologies, Inc.

Inventor： Ron Diamant ,  Gil Stoler ,  Nafea Bshara

IPC: G01R31/28 ,  G01R31/317 ,  G06N20/00

Abstract: An error-handling processing circuit and system are provided. The system can receive an error signal, such as an interrupt, and decouple (e.g., by a gate signal) a functional clock from a processing block, in some instances effectively halting the processing block's operation. This can prevent a cascade of interdependent errors, thereby avoiding producing redundant or confusing error information. The system can include the processing block, a debug clock not coupled to the processing block, and a data block (e.g., a register file) coupled to the debug clock and to an external input/output interface. The data block can be configured to continue receiving a clock signal via a multiplexer from the debug clock without disruption after the functional clock is decoupled, enabling the data block to remain operational for debugging.

公开(公告)号：US20200259759A1

公开(公告)日：2020-08-13

申请号：US16864979

申请日：2020-05-01

Applicant: Amazon Technologies, Inc.

Inventor： Leah Shalev ,  Brian William Barrett ,  Nafea Bshara ,  Georgy Machulsky

IPC: H04L12/863 ,  H04L29/08 ,  H04L12/801 ,  H04L12/861 ,  H04L29/06 ,  H04L1/18 ,  G06F15/173 ,  H04L12/707 ,  H04L12/741

Abstract: Provided are systems and methods for reliable, out-of-order transmission of packets. In some implementations, provided is an apparatus configured to communicate with a network and a host device. The apparatus may receive messages from the host device at a send queue, where each message includes destination information. The apparatus may further determine, using the destination information and an identify of the send queue, a transport context associated with a destination on the network. The apparatus may further, for each message and using the transport context, generate a packet including the message and transmit the packet over the network. The apparatus may further monitor status for each transmitted packet.

公开(公告)号：US20200151137A1

公开(公告)日：2020-05-14

申请号：US16702187

申请日：2019-12-03

Applicant: Amazon Technologies, Inc.

Inventor： Erez Izenberg ,  Leah Shalev ,  Nafea Bshara ,  Guy Nakibly ,  Georgy Machulsky

IPC: G06F15/167 ,  G06F16/22 ,  H04L29/06

Abstract: Apparatus and methods are disclosed herein for remote, direct memory access (RDMA) technology that enables direct memory access from one host computer memory to another host computer memory over a physical or virtual computer network according to a number of different RDMA protocols. In one example, a method includes receiving remote direct memory access (RDMA) packets via a network adapter, deriving a protocol index identifying an RDMA protocol used to encode data for an RDMA transaction associated with the RDMA packets, applying the protocol index to a generate RDMA commands from header information in at least one of the received RDMA packets, and performing an RDMA operation using the RDMA commands.

公开(公告)号：US10430203B1

公开(公告)日：2019-10-01

申请号：US15669813

申请日：2017-08-04

Applicant: Amazon Technologies, Inc.

Inventor： Robert Michael Johnson ,  Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Asif Khan ,  Nafea Bshara ,  Anthony Nicholas Liguori

IPC: G06F13/42 ,  G06F9/4401 ,  G06F9/455

Abstract: Disclosed are techniques regarding aspects of implementing client configurable logic within a computer system. The computer system can be a cloud infrastructure. The techniques can include providing an identifier in response to configuring client configurable logic within the computer system.

公开(公告)号：US10374885B2

公开(公告)日：2019-08-06

申请号：US15377973

申请日：2016-12-13

Applicant: Amazon Technologies, Inc.

Inventor： Anthony Nicholas Liguori ,  Nafea Bshara

IPC: G06F15/177 ,  H04L12/24 ,  H04L29/06 ,  G06F15/167 ,  G06F9/445 ,  G06F9/455 ,  H04L29/08 ,  G06F9/50 ,  H04L12/66 ,  G06F16/00

Abstract: Techniques for reconfiguring a server to perform various hardware functions are disclosed herein. In one embodiment, a server includes a reconfigurable adapter device, where the reconfigurable adapter device includes a reconfigurable resource that is reprogrammable to perform different hardware functions. The server can receive a provisioning request corresponding to a hardware function from a management service. The reconfigurable adapter device can configure the reconfigurable resource according to the hardware function and report the configured hardware function to the server. The reconfigurable resource can be reconfigured using firmware or emulation software.

公开(公告)号：US10298496B1

公开(公告)日：2019-05-21

申请号：US15716036

申请日：2017-09-26

Applicant: Amazon Technologies, Inc.

Inventor： Guy Nakibly ,  Benzi Denkberg ,  Erez Izenberg ,  Nafea Bshara ,  Uri Leder ,  Ofer Frishman

IPC: H04L12/747 ,  H04L12/861 ,  G06F12/0802 ,  H04L29/06 ,  H04L12/931

Abstract: A data or packet processing device such as a network interface controller may include cache control logic that is configured to receive a first request for processing a first data packet associated with the queue identifier, and obtain a set of memory descriptors associated with the queue identifier from the memory. The set of descriptors can be stored in the cache. When a second request for processing a second data packet associated with the queue identifier is received, the cache control logic can determine that the cache is storing memory descriptors for processing the second data packet, and provide the memory descriptors used for processing the second packet.

公开(公告)号：US20190129796A1

公开(公告)日：2019-05-02

申请号：US16160782

申请日：2018-10-15

Applicant: Amazon Technologies, Inc.

Inventor： Ron Diamant ,  Nafea Bshara ,  Yaniv Shapira ,  Guy Nakibly

IPC: G06F11/10 ,  G06F11/20

Abstract: A method for calculating a plurality (M) of redundancy blocks for multiple (N) data blocks of a plurality (D) of words each, the method comprises: receiving the number (M) of redundancy blocks by a calculator that comprises multiple (R) calculation units; configuring the calculator according to M and R; concurrently calculating, if M equals R, by the multiple (R) calculation units of the calculator, R sets of parity vectors, each set includes a plurality (D) of parity vectors; and calculating the plurality (M) of the redundancy blocks based on the R sets of parity vectors.

公开(公告)号：US10223317B2

公开(公告)日：2019-03-05

申请号：US15279232

申请日：2016-09-28

Applicant: Amazon Technologies, Inc.

Inventor： Islam Atta ,  Christopher Joseph Pettey ,  Asif Khan ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Erez Izenberg ,  Nafea Bshara ,  Kypros Constantinides

IPC: G06F13/40 ,  G06F9/445 ,  G06F13/42 ,  G06F15/78

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

公开(公告)号：US10212138B1

公开(公告)日：2019-02-19

申请号：US14980664

申请日：2015-12-28

Applicant: AMAZON TECHNOLOGIES, INC.

Inventor： Ron Diamant ,  Nafea Bshara ,  Leah Shalev ,  Erez Izenberg

IPC: H04L29/08 ,  H04L29/06 ,  H04L9/14

Abstract: A hardware security accelerator includes a configurable parser that is configured to receive a packet and to extract from the packet headers associated with a set of protocols. The security accelerator also includes a packet type detection unit to determine a type of the packet in response to the set of protocols and to generate a packet type identifier indicative of the type of the packet. A configurable security unit includes a configuration unit and a configurable security engine. The configuration unit configures the configurable security engine according to the type of the packet and to content of at least one of the headers extracted from the packet. The configurable security engine performs security processing of the packet to provide at least one security result.