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    Bias circuit for use with divided bit lines
    52.
    发明授权
    Bias circuit for use with divided bit lines 有权

    公开(公告)号：US10819936B2

    公开(公告)日：2020-10-27

    申请号：US16275092

    申请日：2019-02-13

    Applicant: OmniVision Technologies, Inc.

    Inventor： Hiroaki Ebihara ,  Zheng Yang ,  Rui Wang ,  Teijun Dai

    IPC: H04N5/378 ,  H04N5/3745 ,  H04N5/374 ,  H04N5/369

    Abstract: An image sensor includes a pixel array including a plurality of pixels. Each pixel is coupled to generate image data in response to incident light. A bit line is coupled to a column of pixels of the pixel array and is separated into first and second portions. Each portion is coupled to a corresponding portion of rows of pixels of the pixel array. A readout circuit coupled to the bit line to read out the image data from the pixel array. The readout circuit includes a cascode device coupled between the first and second portions of the bit line. The cascode device is coupled to be biased to electrically separate the first and second portions of the bit line from one another such that a capacitance of each portion of the bit line does not affect a settling time of an other portion of the bit line.

    Gray code counting signal distribution system
    53.
    发明授权
    Gray code counting signal distribution system 有权

    公开(公告)号：US10659056B1

    公开(公告)日：2020-05-19

    申请号：US16440279

    申请日：2019-06-13

    Applicant: OmniVision Technologies, Inc.

    Inventor： Satoshi Sakurai ,  Hiroaki Ebihara

    IPC: H03K23/00 ,  H03M1/56 ,  H03M7/16

    Abstract: A counter distribution system includes an N bit counter to receive a first counting clock to generate a plurality of data bits including lower data bits on lower data bit lines and upper data bits on upper data bit lines. The upper data bits include at least one redundant bit to provide error correction for the counter distribution system. A plurality of latches is coupled to the N bit counter. Each one of the lower data bit lines and each one of the upper data bit lines is coupled to at least one of the latches. The latches are arranged into a plurality of groupings of latches. Each grouping of latches is coupled to a respective latch enable signal. Each latch in each grouping of latches is coupled to latch a respective one of the plurality of data bits in response to the respective latch enable signal.

    CMOS IMAGE SENSOR CLAMPING METHOD WITH DIVIDED BIT LINES
    54.
    发明申请
    CMOS IMAGE SENSOR CLAMPING METHOD WITH DIVIDED BIT LINES 审中-公开

    公开(公告)号：US20190268555A1

    公开(公告)日：2019-08-29

    申请号：US16222827

    申请日：2018-12-17

    Applicant: OmniVision Technologies, Inc.

    Inventor： Hiroaki Ebihara

    IPC: H04N5/378 ,  H01L27/146 ,  H04N5/3745

    Abstract: An image sensor includes a pixel array including a plurality of pixels. A bit line is coupled to a column of pixels of the pixel array. The bit line is separated in to a plurality of portions coupled to the column of pixels. The portions of the bit line are electrically isolated from one another. A readout circuit is coupled to a first portion of the bit line coupled to a first portion of rows of pixels from the column of pixels to read image data from the first portion of rows of pixels from the column of pixels. The readout circuit is further coupled to a second portion of the bit line coupled to a second portion of rows of pixels from the column of pixels to read image data from the second portion of rows of pixels from the column of pixels.

    Comparator for double ramp analog to digital converter
    55.
    发明授权
    Comparator for double ramp analog to digital converter 有权

    公开(公告)号：US10326958B2

    公开(公告)日：2019-06-18

    申请号：US16035363

    申请日：2018-07-13

    Applicant: OmniVision Technologies, Inc.

    Inventor： Hiroaki Ebihara ,  Zheng Yang

    IPC: H03K5/24 ,  H04N5/378

    Abstract: Apparatuses and method for an image sensor with increased analog to digital conversion range and reduced noise are described herein. An example method may include disabling a first auto-zero switch of a comparator, the first auto-zero switch coupled to auto-zero a reference voltage input of the comparator, adjusting an auto-zero offset voltage of a ramp voltage provided to the reference voltage input of the comparator, and disabling a second auto-zero switch of the comparator, the second auto-zero switch coupled to auto-zero a bitline input of the comparator.

    Bitline settling improvement and FPN reduction by floating bitline during charge transfer
    56.
    发明授权
    Bitline settling improvement and FPN reduction by floating bitline during charge transfer 有权

    公开(公告)号：US10290673B1

    公开(公告)日：2019-05-14

    申请号：US15853463

    申请日：2017-12-22

    Applicant: OmniVision Technologies, Inc.

    Inventor： Rui Wang ,  Min Qu ,  Hiroaki Ebihara ,  Zhiyong Zhan

    IPC: H04N5/222 ,  H01L27/146 ,  H04N5/378 ,  H04N5/235 ,  H04N5/374

    Abstract: A photodiode is adapted to accumulate image charges in response to incident light. A transfer transistor is coupled between the photodiode and a floating diffusion to transfer the image charges from the photodiode to the floating diffusion. A transfer gate voltage controls the transmission of the image charges from a transfer receiving terminal of the transfer transistor to the floating diffusion. A reset transistor is coupled to supply a supply voltage to the floating diffusion. A source follower transistor is coupled to receive voltage of the floating diffusion from a gate terminal of the source follower and provide an amplified signal to a source terminal of the source follower. A row select transistor is coupled to enable the amplified signal from the SF source terminal and output the amplified signal to a bitline. A bitline enable transistor is coupled to link between the bitline and a bitline source node. The bitline source node is coupled to a blacksun voltage generator. A current source generator is coupled between the bitline source node and a ground. The current source generator provides adjustable current to the bitline source node through a bias transistor controlled by a bias control voltage.

    Bitline settling improvement by using dummy pixels for clamp
    57.
    发明授权
    Bitline settling improvement by using dummy pixels for clamp 有权

    公开(公告)号：US10165210B1

    公开(公告)日：2018-12-25

    申请号：US15909267

    申请日：2018-03-01

    Applicant: OmniVision Technologies, Inc.

    Inventor： Rui Wang ,  Hiroaki Ebihara

    IPC: H04N3/14 ,  H04N5/335 ,  H04N5/367 ,  H04N5/378 ,  H04N5/217 ,  H04N5/235 ,  H04N5/369 ,  H04N5/357 ,  H04N5/3745

    Abstract: A photodiode is adapted to accumulate image charges in response to incident light. A transfer transistor is coupled between the photodiode and a floating diffusion to transfer the image charges accumulated in the photodiode to the floating diffusion. A reset transistor is coupled to supply a supply voltage to the floating diffusion. A source follower transistor is coupled to receive voltage of the floating diffusion from a SF gate terminal and provide an amplified signal to a source follower source terminal. A row select transistor is coupled to receive the amplified signal from the SF source terminal and output the amplified signal to a bitline. A bitline enable transistor controlled by a bitline enable voltage is coupled to link between the bitline and a bitline source node. The bitline is coupled to an idle voltage generator, a blacksun voltage generator, and a clamp voltage generator. These three voltage generators are each constructed out of a plurality of modified dummy pixels based on the dummy pixels in the dummy rows of an image sensor pixel array.

    Comparator for double ramp analog to digital converter
    58.
    发明授权
    Comparator for double ramp analog to digital converter 有权

    公开(公告)号：US10079990B2

    公开(公告)日：2018-09-18

    申请号：US15277648

    申请日：2016-09-27

    Applicant: OmniVision Technologies, Inc.

    Inventor： Hiroaki Ebihara ,  Zheng Yang

    IPC: H04N5/378 ,  H03K5/24

    CPC classification number: H04N5/378 ,  H03K5/2481

    Abstract: Apparatuses and method for an image sensor with increased analog to digital conversion range and reduced noise are described herein. An example method may include disabling a first auto-zero switch of a comparator, the first auto-zero switch coupled to auto-zero a reference voltage input of the comparator, adjusting an auto-zero offset voltage of a ramp voltage provided to the reference voltage input of the comparator, and disabling a second auto-zero switch of the comparator, the second auto-zero switch coupled to auto-zero a bitline input of the comparator.

    Feedback capacitor formed by bonding-via in pixel level bond
    59.
    发明授权
    Feedback capacitor formed by bonding-via in pixel level bond 有权

    公开(公告)号：US09859312B1

    公开(公告)日：2018-01-02

    申请号：US15427928

    申请日：2017-02-08

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Rui Wang ,  Hiroaki Ebihara ,  Zheng Yang ,  Chun-Ming Tang ,  Chao-Fang Tsai ,  Tiejun Dai

    IPC: H01L27/146

    CPC classification number: H01L27/14603 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464

    Abstract: An image sensor includes a photodiode disposed in a first semiconductor material, and the photodiode is positioned to absorb image light through the backside of the first semiconductor material. A first floating diffusion is disposed proximate to the photodiode and coupled to receive image charge from the photodiode in response to a transfer signal applied to a transfer gate disposed between the photodiode and the first floating diffusion. A second semiconductor material, including a second floating diffusion, is disposed proximate to the frontside of the first semiconductor material. A dielectric material is disposed between the first semiconductor material and the second semiconductor material, and includes a first bonding via extending from the first floating diffusion to the second floating diffusion, a second bonding via disposed laterally proximate to the first bonding via, and a third bonding via disposed laterally proximate to the first bonding via.

    Dynamic current control for column ADC
    60.
    发明授权
    Dynamic current control for column ADC 有权

    公开(公告)号：US12199632B2

    公开(公告)日：2025-01-14

    申请号：US18176373

    申请日：2023-02-28

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Hiroaki Ebihara ,  Chengcheng Xu ,  Satoshi Sakurai ,  Kenny Geng

    IPC: H03M1/46

    Abstract: A tail current source of a comparator includes a first transistor and a second transistor configured to operate as current sources, wherein the first and second transistors are coupled between a tail node of the comparator and a voltage node, and wherein the tail comprises a node coupled to first and second inputs of the comparator. The tail current source also includes a switch configured to selectively couple the second transistor between the tail and the voltage node, and a bias voltage source coupled to gates of the first and second transistors. The switch is configured to be on during an analog-to-digital conversion (ADC) reset signal period and an ADC image signal period, and the switch is configured to be off during an auto-zero period, a period between the ADC reset signal and image signal periods, and a period after the ADC image signal period.

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