公开(公告)号：US20200303361A1

公开(公告)日：2020-09-24

申请号：US16360619

申请日：2019-03-21

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： SHING-YIH SHIH

IPC: H01L25/18 ,  H01L21/822 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L23/48 ,  H01L25/00

Abstract: The present disclosure provides a semiconductor package structure. The semiconductor package structure includes a first die, a second die and a hybrid bonding structure disposed between the first die and the second die. The first die includes a first front side and a first back side opposite to the first front side. The second die includes a second front side and a second back side opposite to the second front side. The hybrid bonding structure is disposed between the first back side of the first die and the second front side of the second die. The first die and the second die are bonded to each other by the hybrid bonding structure. The hybrid bonding structure includes an organic barrier layer and an inorganic barrier layer bonded to each other.

公开(公告)号：US20200286777A1

公开(公告)日：2020-09-10

申请号：US16389644

申请日：2019-04-19

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： MAO-YING WANG ,  SHING-YIH SHIH ,  HUNG-MO WU ,  YUNG-TE TING ,  YU-TING LIN

IPC: H01L21/768 ,  H01L23/522

Abstract: The present disclosure provides a method for preparing an interconnect structure. One aspect of the present disclosure provides a method for preparing an interconnect structure. The method includes the following steps. A first dielectric layer is provided over a first connecting line. A first upper via opening is formed in the first dielectric layer, wherein the first upper via opening has a first width. A first lower via opening is formed in the first dielectric layer, wherein the first lower via opening is formed under and coupled to the first upper via opening. The first lower via opening has a second width less than the first width of the first upper via opening. A connecting via is formed in the first upper via opening and the first lower via opening. A second connecting line is formed over the connecting via.

公开(公告)号：US20200286775A1

公开(公告)日：2020-09-10

申请号：US16291376

申请日：2019-03-04

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： MAO-YING WANG ,  SHING-YIH SHIH ,  HUNG-MO WU ,  YUNG-TE TING ,  YU-TING LIN

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: The present disclosure provides an interconnect structure. The interconnect structure includes a first connecting line, a second connecting line disposed over the first connecting line, and a connecting via disposed in a dielectric structure between the first connecting line and the second connecting line, and electrically connecting the first connecting line and the second connecting line. The connecting via includes a head portion and a body portion, and a width of the head portion is greater than a width of the body portion.

公开(公告)号：US20200090980A1

公开(公告)日：2020-03-19

申请号：US16130348

申请日：2018-09-13

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： SHING-YIH SHIH

IPC: H01L21/762 ,  H01L21/02

Abstract: The present disclosure provides a method for preparing semiconductor structures. The method includes the following steps. A substrate is provided. A plurality of first trenches are formed in the substrate. A first initially-flowable layer is formed in the plurality of first trenches. A top surface of the first initially-flowable layer is lower than openings of the plurality of first trenches. A first treatment is performed on the first initially-flowable layer to form a first dielectric layer in the plurality of first trenches. A second initially-flowable layer is formed to fill the plurality of first trenches. A second treatment is performed on the second initially-flowable layer to form a second dielectric layer in the plurality of first trenches.