公开(公告)号：US07933521B2

公开(公告)日：2011-04-26

申请号：US11943817

申请日：2007-11-21

Applicant: Zhenli Wen ,  Kevin Zhang ,  Dongsheng Han ,  Fahua Lan

Inventor： Zhenli Wen ,  Kevin Zhang ,  Dongsheng Han ,  Fahua Lan

IPC: H04J14/02 ,  H04B10/00

CPC classification number: G02B6/29367 ,  G02B6/2938 ,  G02B6/4246

Abstract: An apparatus for use in an optical transceiver module that incorporates an integrated multiplexer/demultiplexer for high speed data transfer applications. One example embodiment includes a transmissive block arranged to interface with a transmit optical port, a receive optical port, and a plurality of optical subassemblies. The transmit optical port may transmit a first multiplexed optical signal and the receive optical port may receive a second multiplexed optical signal. Filters may be positioned between the transmissive block and one or more of the optical subassemblies to transmit signals at predetermined wavelengths while reflecting other signals incident thereon.

Abstract translation: 一种用于光收发器模块的装置，其包括用于高速数据传输应用的集成多路复用器/解复用器。 一个示例实施例包括布置成与发射光端口，接收光端口和多个光学子组件接口的透射块。 发射光端口可以发送第一复用光信号，并且接收光端口可以接收第二复用光信号。 滤波器可以位于透射块和一个或多个光学子组件之间，以以预定波长传输信号，同时反射入射在其上的其它信号。

公开(公告)号：US07924596B2

公开(公告)日：2011-04-12

申请号：US11861293

申请日：2007-09-26

Applicant: Zhanping Chen ,  Kevin Zhang

Inventor： Zhanping Chen ,  Kevin Zhang

IPC: G11C17/00

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: A programmable ROM (PROM) architecture includes cascode NMOS transistors with a fuse bit cell that is arrayed, with sleep transistors located in each column of the array that in a standby mode shut down the entire fuse array. A fuse redundancy scheme may be used to repair a defective fuse row.

Abstract translation: 可编程ROM（PROM）架构包括具有排列的熔丝位单元的级联NMOS晶体管，其中位于阵列的每列中的休眠晶体管在待机模式下关闭整个熔丝阵列。 熔丝冗余方案可用于修复有缺陷的熔丝排。

公开(公告)号：US20090257714A1

公开(公告)日：2009-10-15

申请号：US12103365

申请日：2008-04-15

Applicant: Kevin Zhang ,  Guojun Lai ,  Youjian Wu ,  Fahua Lan

Inventor： Kevin Zhang ,  Guojun Lai ,  Youjian Wu ,  Fahua Lan

IPC: G02B6/32

CPC classification number: G02B6/327 ,  G02B6/14

Abstract: A glass optical reflective tap is described that optically connects two optical fibers and may tap a portion of the light that is being communicated between the optical fibers. In one embodiment of the invention, the optical filter includes two D-lenses that operate as focusing or collimator lenses. The first D-lens focuses an optical signal onto a tap filter that allows a majority of the light within an optical signal to pass and also reflects a small portion of optical signal light to a reflective port. The second D-lens focuses the passed light into a transmission port of an optical fiber.

Abstract translation: 描述了玻璃光学反射抽头，其光学地连接两根光纤并且可以抽出正在光纤之间连通的一部分光。 在本发明的一个实施例中，滤光器包括作为聚焦或准直透镜操作的两个D透镜。 第一个D透镜将光信号聚焦到抽头滤波器上，允许光信号内的大部分光通过，并将一小部分光信号光反射到反射端口。 第二个D镜头将通过的光线聚焦到光纤的传输端口。

公开(公告)号：US07602663B2

公开(公告)日：2009-10-13

申请号：US11644381

申请日：2006-12-22

Applicant: Zhanping Chen ,  Jonathan P. Douglas ,  Praveen Mosalikanti ,  Kevin Zhang ,  Gregory F. Taylor

Inventor： Zhanping Chen ,  Jonathan P. Douglas ,  Praveen Mosalikanti ,  Kevin Zhang ,  Gregory F. Taylor

IPC: G11C17/18

CPC classification number: G11C17/16 ,  G11C17/14 ,  G11C17/18 ,  G11C29/816

Abstract: A plurality of fuse cells are arranged in an array. One or more fuse cells include a pair of fuse devices to output a pair of voltages, respectively, wherein the pair of fuse devices are redundantly programmed. A sense amplifier is coupled to the plurality of fuse cells to read the pair of voltage outputs from each of the plurality of fuse cells, respectively. A comparator circuit is coupled to the sense amplifier to compare the pair of voltage outputs for each of the plurality of fuse cells and to output the compared result.

Abstract translation: 多个熔丝单元被布置成阵列。 一个或多个保险丝单元包括分别输出一对电压的一对熔丝器件，其中该对熔丝器件被冗余编程。 感测放大器耦合到多个熔丝单元以分别从多个熔丝单元中的每一个读出一对电压输出。 比较器电路耦合到读出放大器以比较多个熔丝单元中的每一个的一对电压输出并输出比较结果。

公开(公告)号：US20090080232A1

公开(公告)日：2009-03-26

申请号：US11861293

申请日：2007-09-26

Applicant: Zhanping Chen ,  Kevin Zhang

Inventor： Zhanping Chen ,  Kevin Zhang

IPC: G11C17/00

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: A programmable ROM (PROM) architecture includes cascode NMOS transistors with a fuse bit cell that is arrayed, with sleep transistors located in each column of the array that in a standby mode shut down the entire fuse array. A fuse redundancy scheme may be used to repair a defective fuse row.

Abstract translation: 可编程ROM（PROM）架构包括具有排列的熔丝位单元的级联NMOS晶体管，其中位于阵列的每列中的休眠晶体管在待机模式下关闭整个熔丝阵列。 熔丝冗余方案可用于修复有缺陷的熔丝排。

公开(公告)号：US07354203B2

公开(公告)日：2008-04-08

申请号：US11178624

申请日：2005-07-11

Applicant: Stefan Pfnuer ,  Tengda Du ,  Kevin Zhang ,  Julie S. Eng ,  Axel Mehnert

Inventor： Stefan Pfnuer ,  Tengda Du ,  Kevin Zhang ,  Julie S. Eng ,  Axel Mehnert

IPC: G02B6/36

CPC classification number: G02B6/4201 ,  G02B6/36 ,  G02B6/4251

Abstract: A package for maintaining alignment of components includes a frame and a beam with the beam attached to the frame and one end of the beam. One or more components are mounted to the beam. The frame and a portion of the beam are separated from each other by a channel which allows portions of the beam to flex substantially independently of the frame when a force is applied to the frame. Thus, the effects resulting from forces applied to the frame are not experienced by the beam, or are at least attenuated, so that the alignment of the components mounted on the beam is substantially preserved.

Abstract translation: 用于维持部件对准的包装件包括框架和梁，其中梁连接到框架和梁的一端。 一个或多个部件安装到梁上。 框架和梁的一部分通过通道分开，该通道允许当力施加到框架时梁的一部分基本上独立于框架弯曲。 因此，由施加到框架的力产生的影响不受梁的影响，或者至少被衰减，使得安装在梁上的部件的对准被基本保持。

公开(公告)号：US07317851B2

公开(公告)日：2008-01-08

申请号：US10724471

申请日：2003-11-26

Applicant: Johnny Zhong ,  Steve Wang ,  Ping Xie ,  Kevin Zhang

Inventor： Johnny Zhong ,  Steve Wang ,  Ping Xie ,  Kevin Zhang

IPC: G02B6/26 ,  G02B6/28

CPC classification number: G02B6/29367 ,  G02B6/29383 ,  G02B6/3897 ,  G02B27/1073 ,  G02B27/145 ,  H04J14/0201

Abstract: An optical add/drop patch cord. The optical add/drop patch cord has an optical add/drop component enclosed by a casing. An input fiber is optically coupled to the optical add/drop component and permanently or detachably connected to the casing. A drop fiber is optically coupled to the optical add/drop component and permanently or detachably connected to the casing. An add fiber is optically coupled to the optical add/drop component and permanently connected to the casing. An output fiber is optically coupled to the optical add/drop component and permanently connected to the casing.

Abstract translation: 光分插拨号线。 光学分插拨号线具有由壳体包围的光学分插部件。 输入光纤光耦合到光学分插部件并且永久地或可拆卸地连接到壳体。 液滴光纤光学耦合到光学分插部件并且永久地或可拆卸地连接到壳体。 添加光纤光学耦合到光学分插部件并且永久地连接到壳体。 输出光纤光学耦合到光学分插部件并且永久地连接到壳体。

公开(公告)号：US06707752B2

公开(公告)日：2004-03-16

申请号：US09887870

申请日：2001-06-22

Applicant: Kevin Zhang

Inventor： Kevin Zhang

IPC: G11C500

CPC classification number: G06F12/0895 ,  Y02D10/13

Abstract: A memory and method for accessing data in a memory which uses non redundant-form address decoders is disclosed. Lines in subarrays of the memory are selected using the redundant-form addresses. The least significant bit of the non redundant-form address is used to select between these lines. The compare function of the cache memory is then done with a non redundant-form address.

Abstract translation: 公开了一种用于访问使用非冗余形式地址解码器的存储器中的数据的存储器和方法。 使用冗余表单地址选择存储器子阵列中的行。 非冗余形式地址的最低有效位用于在这些行之间进行选择。 然后使用非冗余形式的地址来完成高速缓冲存储器的比较功能。

公开(公告)号：US06181608B2

公开(公告)日：2001-01-30

申请号：US09261915

申请日：1999-03-03

Applicant: Ali Keshavarzi ,  Kevin Zhang ,  Yibin Ye ,  Vivek K. De

Inventor： Ali Keshavarzi ,  Kevin Zhang ,  Yibin Ye ,  Vivek K. De

IPC: G11C1134

CPC classification number: G11C11/412 ,  G11C11/418

Abstract: In some embodiments, the invention includes an integrated circuit including a bitline and a bitline#, wordlines, and memory cells. The memory cells each corresponding to one of the wordlines and each include first and second pass transistors coupled between first and second storage nodes, respectively, and the bitline and bitline#, respectively, the corresponding wordline being coupled to gates of the first and second pass transistors. The memory cells include first and second inverters cross-coupled between the first and second storage nodes, wherein the first and second pass transistors each have a lower threshold voltage than do transistors of the first and second inverters. Wordline voltage control circuitry coupled to the wordlines selectively controls wordline signals on the wordlines. In some embodiments, the wordline voltage control circuitry asserts the wordline signal for a selected wordline corresponding to a memory cell selected to be read and underdrives the wordline signals for the wordlines not corresponding to the selected memory cell.

Abstract translation: 在一些实施例中，本发明包括包括位线和位线＃，字线和存储器单元的集成电路。 每个对应于一个字线的存储单元分别包括分别耦合在第一和第二存储节点之间的第一和第二传输晶体管，位线和位线＃分别耦合到第一和第二通道的栅极 晶体管。 存储单元包括交叉耦合在第一和第二存储节点之间的第一和第二反相器，其中第一和第二传输晶体管每个具有比第一和第二反相器的晶体管更低的阈值电压。 耦合到字线的字线电压控制电路有选择地控制字线上的字线信号。 在一些实施例中，字线电压控制电路为对应于被选择要读取的存储器单元选择的字线断言字线信号，并驱动不对应于所选存储单元的字线的字线信号。