公开(公告)号：US20100207582A1

公开(公告)日：2010-08-19

申请号：US12670393

申请日：2008-09-27

申请人： Zhengdong Wu ,  Jun Zhou ,  Qinyao Yang

发明人： Zhengdong Wu ,  Jun Zhou ,  Qinyao Yang

IPC分类号： H02J7/00

CPC分类号： H02J7/0026 ,  H01M10/425 ,  H01M10/441 ,  H01M2010/4271

摘要： A multi-cell protection circuit and method. The multi-cell protection circuit comprises one or more multi-cell protection chips, a charge control switch (M2) and a discharge control switch (M1). Each multi-cell protection chip comprises a multi-cell protection integrated circuit module and an expansion connection module. The input terminals (VC1, VC2, VC3, GND1, VC4, VC5, VC6, VC7, GND) of the multi-cell protection integrated circuit module are connected to the positive and negative poles of corresponding cells. The output terminals (co, do) of the multi-cell protection integrated circuit module are connected to the interior signal input terminals (Dco, Ddo) of the expansion connection module. The expansion signal input terminals (exterior.co, exterior.do) of the expansion connection module are connected to expansion signal output terminals (Co′, Do′) of an expansion connection module in a multi-cell protection chip adjacent to this multi-cell protection chip. The output terminals (Co′, Do′) of the expansion connection module in the last multi-cell protection chip among the multi-cell protection chips connected in the multi-cell protection circuit are connected to the charge control switch and the discharge control switch, respectively.

摘要翻译： 多单元保护电路及方法。 多单元保护电路包括一个或多个多电池保护芯片，充电控制开关（M2）和放电控制开关（M1）。 每个多单元保护芯片包括多单元保护集成电路模块和扩展连接模块。 多单元保护集成电路模块的输入端子（VC1，VC2，VC3，GND1，VC4，VC5，VC6，VC7，GND）连接到相应单元的正极和负极。 多单元保护集成电路模块的输出端子（co，do）连接到扩展连接模块的内部信号输入端子（Dco，Ddo）。 扩展连接模块的扩展信号输入端子（exterior.co，exterior.do）连接到与该多路复用器相邻的多单元保护芯片中的扩展连接模块的扩展信号输出端（Co'，Do' 电池保护芯片。 连接在多单元保护电路中的多单元保护芯片中的最后多单元保护芯片中的扩展连接模块的输出端子（Co'，Do'）连接到充电控制开关和放电控制开关 ， 分别。

公开(公告)号：US07747789B2

公开(公告)日：2010-06-29

申请号：US11569305

申请日：2006-04-20

申请人： Jun Zhou

发明人： Jun Zhou

IPC分类号： G06F3/00

CPC分类号： H04L5/1438 ,  H04L27/2602

摘要： Embodiments of the present invention discloses a method for selecting an operating mode including the steps: a first station transmits downlink handshake signals to a second station; the second station acquires the information of the downlink handshake signals and transmits the acquired information to the first station; the first station selects an operating mode according to the received information. The downlink handshake signal includes the border tones in each mode and supported by both the first station and the second station. The present invention reduces the time of selecting an operating mode and further ensures that the xDSL network operating mode according with the requirements of practical services can be selected.

摘要翻译： 本发明的实施例公开了一种选择操作模式的方法，包括以下步骤：第一站向第二站发送下行握手信号; 第二站获取下行握手信号的信息，并将获取的信息发送到第一站; 第一站根据接收到的信息选择操作模式。 下行握手信号包括每种模式中的边界音，并由第一站和第二站支持。 本发明减少了选择操作模式的时间，并进一步确保可以选择符合实际服务要求的xDSL网络操作模式。

公开(公告)号：US20100081308A1

公开(公告)日：2010-04-01

申请号：US12586787

申请日：2009-09-28

申请人： Leland Wang ,  Shih-Chi Hsiao ,  Jin-Liang Du ,  Jun Zhou ,  Zheng-Wang Wu ,  Shuo-Bin Ru

发明人： Leland Wang ,  Shih-Chi Hsiao ,  Jin-Liang Du ,  Jun Zhou ,  Zheng-Wang Wu ,  Shuo-Bin Ru

IPC分类号： H01R13/64

CPC分类号： H01R13/7033 ,  H01R12/57 ,  H01R24/46 ,  H01R24/50 ,  H01R2103/00 ,  Y10S439/944

摘要： A RF connector comprising: an insulative housing defining a space section; an upper fixed contact and a lower movable contact are disposed on two opposite sides of the housing in a first direction, each of said upper fixed contact and said lower movable contact including a contact section in the space section and a solder tail exposed outside of the housing, the lower movable contact having on two opposite sides a pair of bending ends disposed which is a lying U-shape; and an upper case mounted upon the housing and defining a plug insertion passageway; and a metallic shell enclosing said upper case and the housing.

公开(公告)号：US07688744B2

公开(公告)日：2010-03-30

申请号：US11570998

申请日：2005-07-20

申请人： Tao Yang ,  Jun Zhou ,  Zhiguo Yan ,  Ruijie Xiao

发明人： Tao Yang ,  Jun Zhou ,  Zhiguo Yan ,  Ruijie Xiao

IPC分类号： G01R31/08

CPC分类号： H04M3/304 ,  H04M11/062

摘要： A broadband test line-access board includes at least two broadband test line-access units. Each of the at least two broadband test line-access units includes first, second, and third test terminals, a signal splitter, first, second, and third switches, and first second and third interface terminals. The broadband test line-access board further includes a set of inner test buses, including an internal inner-test bus, an internal outer-test bus and an internal auxiliary-test bus, and fourth, fifth, and sixth switches, and a low-pass filter.

摘要翻译： 宽带测试线路接入板包括至少两个宽带测试线路接入单元。 所述至少两个宽带测试线路访问单元中的每一个包括第一测试终端，第二测试终端和第三测试终端，信号分离器，第一，第二和第三交换机以及第一第二和第三接口终端。 宽带测试线路接入板还包括一组内部测试总线，包括内部内部测试总线，内部外部测试总线和内部辅助测试总线，以及第四，第五和第六个开关，低 通过滤波器

公开(公告)号：US20100031215A1

公开(公告)日：2010-02-04

申请号：US12183898

申请日：2008-07-31

申请人： William D. Ramsour ,  Samuel I. Ward ,  Jun Zhou

发明人： William D. Ramsour ,  Samuel I. Ward ,  Jun Zhou

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A method for generating an electronic circuit layout with placed circuit elements receives a user provided schematic, the user provided schematic comprising a plurality of circuit elements, each circuit element comprising general parameters. The method associates a plurality of first placement parameters with each of the plurality of circuit elements, wherein the first placement parameters comprise a cell horizontal position, a cell vertical stacking position, and a cell vertical adjacent spacing. The method retrieves, from a design library, design parameters associated with at least one of the plurality of circuit elements. The method assigns first absolute placement coordinates for each of the plurality of circuit elements based on the first placement parameters and the design parameters. The method defines and performs an adjustment operation on the placement parameters of a selected subset of circuit elements, generating adjusted placement parameters. The method assigns second absolute placement coordinates based on the first placement parameters, the design parameters, and the adjusted placement parameters and generates an electronic circuit layout with placed circuit elements based on the second absolute placement coordinates.

摘要翻译： 用于产生具有放置的电路元件的电子电路布局的方法接收用户提供的原理图，用户提供了包括多个电路元件的示意图，每个电路元件包括一般参数。 该方法将多个第一放置参数与多个电路元件中的每一个相关联，其中第一放置参数包括单元水平位置，单元垂直堆叠位置和单元垂直相邻间隔。 该方法从设计库检索与多个电路元件中的至少一个相关联的设计参数。 该方法基于第一放置参数和设计参数为多个电路元件中的每一个分配第一绝对放置坐标。 该方法定义并执行对所选择的电路元件子集的放置参数的调整操作，生成调整的放置参数。 该方法基于第一放置参数，设计参数和调整的放置参数分配第二绝对放置坐标，并且基于第二绝对放置坐标生成具有放置的电路元件的电子电路布局。

公开(公告)号：US20090210849A1

公开(公告)日：2009-08-20

申请号：US12032643

申请日：2008-02-16

申请人： Yiu-Hing Chan ,  Ronald Dennis Rose ,  Jun Zhou

发明人： Yiu-Hing Chan ,  Ronald Dennis Rose ,  Jun Zhou

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Disclosed is a method of estimating interconnect wire parasitics in integrated circuits which includes obtaining a circuit layout having circuit components placed thereon including source input/output (I/O) pins and sink I/O pins, the circuit layout having a circuit hierarchy, bubbling up of the I/O pins until all I/O pins are on a same level of the circuit hierarchy, and then estimating interconnect segments to be employed in interconnecting at least some circuit components of the placed circuit components of the circuit layout. Also disclosed is a circuit design system and program storage device.

摘要翻译： 公开了一种估计集成电路中的互连线寄生效应的方法，其包括获得具有放置在其上的电路组件的电路布局，其中包括源输入/输出（I / O）引脚和吸收器I / O引脚，电路布局具有电路层级，冒泡 直到所有I / O引脚都位于电路层级的相同电平上，然后估计互连线段，用于互连电路布局放置的电路元件的至少一些电路元件。 还公开了电路设计系统和程序存储装置。

公开(公告)号：US20080298262A1

公开(公告)日：2008-12-04

申请号：US11570998

申请日：2005-07-20

申请人： Tao Yang ,  Jun Zhou ,  Zhiguo Yan ,  Ruijie Xiao

发明人： Tao Yang ,  Jun Zhou ,  Zhiguo Yan ,  Ruijie Xiao

IPC分类号： G06F11/00

CPC分类号： H04M3/304 ,  H04M11/062

摘要： A broadband test line-access unit, including a first test terminal, a second test terminal, a third test terminal, a signal splitter, a first switch, a second switch, a third switch, a first interface terminal, a second interface terminal and a third interface terminal. A broadband test line-access board, including at least two broadband test line-access units, a set of internal test buses, a fourth switch, a fifth switch and a sixth switch, the set of internal test buses including an internal inner-test bus, an internal outer-test bus and an internal auxiliary-test bus. A broadband test device, including at least one broadband test line-access boards, an eighth switch, a ninth switch, a test control module. The broadband test device is of simple structure and low cost, facilitates a port level N+1 backup function within a board, and thus can provide improved communication reliability.

摘要翻译： 一种宽带测试线路接入单元，包括第一测试终端，第二测试终端，第三测试终端，信号分离器，第一交换机，第二交换机，第三交换机，第一接口终端，第二接口终端和 第三接口终端。 一种宽带测试线路接入板，包括至少两个宽带测试线路接入单元，一组内部测试总线，第四开关，第五开关和第六开关，所述内部测试总线包括内部内部测试 总线，内部外部测试总线和内部辅助测试总线。 一种宽带测试设备，包括至少一个宽带测试线路接入板，第八交换机，第九交换机，测试控制模块。 宽带测试设备结构简单，成本低，便于板内的端口级N + 1备份功能，从而提高通信可靠性。

公开(公告)号：US20080167838A1

公开(公告)日：2008-07-10

申请号：US11968322

申请日：2008-01-02

申请人： Guozhu Long ,  Dong Wei ,  Jun Zhou ,  Jianhua Liu

发明人： Guozhu Long ,  Dong Wei ,  Jun Zhou ,  Jianhua Liu

IPC分类号： G06F17/18 ,  H04B15/00 ,  H04B1/38

CPC分类号： H04L1/20 ,  H04L27/2601

摘要： A network component comprising at least one processor configured to implement a method comprising creating a bivariate histogram using impulse noise data comprising a plurality of variables, wherein the bivariate histogram describes the joint statistics between at least two of the variables. Also disclosed is an apparatus comprising an impulse noise monitor (INM) in communication with an impulse noise sensor (INS), wherein the INM is configured to receive error data from the INS and create a bivariate histogram comprising a plurality of variables using the error data. Included is a method comprising providing a bivariate histogram comprising an impulse noise length (IL) and an impulse noise inter-arrival time (IAT) for a plurality of impulse noise events, wherein the IL and the IAT are each measured in integer multiples of discrete multi-tone symbols, and wherein the bivariate histogram is used to determine a minimum impulse noise protection.

摘要翻译： 一种网络组件，包括至少一个处理器，其被配置为实现包括使用包括多个变量的脉冲噪声数据创建双变量直方图的方法，其中所述双变量直方图描述了至少两个变量之间的联合统计。 还公开了一种包括与脉冲噪声传感器（INS）通信的脉冲噪声监测器（INM）的装置，其中，INM被配置为从INS接收错误数据，并使用误差数据创建包括多个变量的双变量直方图 。 包括提供包括用于多个脉冲噪声事件的脉冲噪声长度（IL）和脉冲噪声到达间隔时间（IAT））的双变量直方图的方法，其中IL和IAT各自以离散的整数倍进行测量 多音调符号，并且其中使用双变量直方图来确定最小脉冲噪声保护。

公开(公告)号：US07325210B2

公开(公告)日：2008-01-29

申请号：US11077043

申请日：2005-03-10

申请人： Vasant Rao ,  Cindy Washburn ,  Jun Zhou ,  Jeffrey P. Soreff ,  Patrick M. Williams ,  David J. Hathaway

发明人： Vasant Rao ,  Cindy Washburn ,  Jun Zhou ,  Jeffrey P. Soreff ,  Patrick M. Williams ,  David J. Hathaway

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5031 ,  G06F17/5068

摘要： A hybrid linear wire model for tuning the transistor widths of circuits linked by RC interconnects is described. The method uses two embedded simulators during the tuning process on netlists that contain resistors (Rs). A Timing oriented simulator is used only for timing purposes on the original netlist that includes all the Rs. A Gradient oriented simulator is then run only on the modified netlist with all Rs shorted and within the iterative loop of the tuner to compute gradients. The present hybrid method achieves a significant improvement in computational speed. The Timing oriented simulator is fast and accurate for only timing netlists with Rs, but cannot compute gradients efficiently. The Gradient oriented simulator computes gradients efficiently but cannot do so in the presence of Rs. To prevent “de-tuning” that typically occurs when all Rs are shorted, ‘wire-adjusts’ are provided that make the initial timing results using the Gradient oriented simulator on the shorted netlist match the timing results using Timing oriented simulator on the original netlist. This permits the optimizer sense initially the correct set of critical timing paths, and more significantly, it permits the wire-adjusts keep track of the changing transistor widths to guide the optimizer during the iterations until convergence is achieved.

摘要翻译： 描述了用于调谐由RC互连链接的电路的晶体管宽度的混合线性线模型。 在调谐过程中，该方法使用两个嵌入式模拟器，其中包含电阻（Rs）。 面向计时的模拟器仅用于包含所有Rs的原始网表的时序目的。 然后，一个面向梯度的模拟器仅在修改后的网表上运行，所有的Rs都已经短路，并在调谐器的迭代循环内计算梯度。 目前的混合方法实现了计算速度的显着提高。 面向时序的模拟器只需要具有Rs的时间网络列表即可快速准确，但无法有效地计算渐变。 梯度导向模拟器有效地计算梯度，但在Rs的存在下不能这样做。 为了防止所有Rs短路时通常发生的“去调谐”，提供“线调整”，使得在短路网表上使用面向梯度的模拟器的初始定时结果与使用定时模型的原始网表上的定时结果相匹配 。 这允许优化器最初感测正确的关键定时路径集合，并且更重要的是，它允许线路调整跟踪改变的晶体管宽度，以在迭代期间引导优化器直到实现收敛。

公开(公告)号：US20070177552A1

公开(公告)日：2007-08-02

申请号：US10589323

申请日：2006-01-12

申请人： Wangjun Wu ,  Chengdong Yu ,  Zhu Tan ,  Tao Pu ,  Wensheng He ,  Peng Lan ,  Jun Zhou ,  Ming Yu

发明人： Wangjun Wu ,  Chengdong Yu ,  Zhu Tan ,  Tao Pu ,  Wensheng He ,  Peng Lan ,  Jun Zhou ,  Ming Yu

IPC分类号： H04B7/216

CPC分类号： H04W88/08

摘要： The present invention discloses a distributed base station system as well as its networking method and base band unit. In this system, the base band unit (BBU) and RF unit (RFU) of the base station are separated, and the RFU is equipped with base band RF interfaces for interconnecting the BBU and transmitting data information, thereby forming the base station. Based on the separation of the BBU from the RFU, the BBU capacity is further divided at the same time, and every unit is also arranged independently. The BBU networking and capacity expansion may be achieved with capacity expansion interfaces and base band RF interfaces provided by BBU interface units in flexible and convenient ways.

摘要翻译： 本发明公开了一种分布式基站系统及其组网方法和基带单元。 在该系统中，基站的基带单元（BBU）和RF单元（RFU）被分离，并且RFU配备有用于互连BBU并发送数据信息的基带RF接口，从而形成基站。 基于BBU与RFU的分离，BBU容量同时进一步划分，每个单元也独立安排。 BBU网络和容量扩展可以通过容量扩展接口和BBU接口单元以灵活方便的方式提供的基带RF接口来实现。