公开(公告)号：US11100858B2

公开(公告)日：2021-08-24

申请号：US16688551

申请日：2019-11-19

Applicant: Samsung Display Co., Ltd.

Inventor： Jun-yong An ,  Jaewon Kim ,  Hyunae Park ,  Hyungjun Park ,  Seungwoo Sung ,  Young-soo Yoon ,  Ji-eun Lee ,  Yun-kyeong In ,  Donghyeon Jang ,  Junyoung Jo

IPC: G09G3/36 ,  G09G3/3233 ,  H01L27/32

Abstract: A display device includes: a display panel in which a non-display region and a display region surrounding the non-display region are defined, wherein the display panel includes: a base layer comprising a first region in which a hole is defined corresponding to the non-display region, a second region surrounding the first region, and a third region corresponding to the display region; and first signal line parts disposed on the second region and the third region, the first signal line parts arrayed spaced apart from each other in a first direction, and each of the first signal line parts includes: a first line; a second line spaced apart from the first line; and a first connection part configured to connect the first line and the second line.

公开(公告)号：US20200176550A1

公开(公告)日：2020-06-04

申请号：US16524177

申请日：2019-07-29

Applicant: Samsung Display Co., Ltd.

Inventor： Ilgoo Youn ,  Jaewon Kim ,  Hyunae Park ,  Hyungjun Park ,  Seungwoo Sung ,  Junyong An ,  Nuree Um ,  Youngsoo Yoon ,  Jieun Lee ,  Seunghan Jo

IPC: H01L27/32

Abstract: A display device including: a substrate including a display area, a peripheral area, and a pad area; a first main voltage line in the peripheral area, and a first connector extending from the first main voltage line to the pad area; and a second main voltage line in the peripheral area, and a second connector extending from the second main voltage line to the pad area, wherein each of the first connector and the second connector includes a first and second layer overlapping each other with a first insulating layer therebetween, the first insulating layer is in the display area and the peripheral area, the peripheral area includes an open area exposing the first and second connector and surrounding the display area, and the first insulating layer includes slits between the first and second connector and extending from an end of the first insulating layer toward the display area.

公开(公告)号：US20200176526A1

公开(公告)日：2020-06-04

申请号：US16698864

申请日：2019-11-27

Applicant: Samsung Display Co., Ltd.

Inventor： Youngsoo Yoon ,  Jaewon Kim ,  Hyunae Park ,  Hyungjun Park ,  Seungwoo Sung ,  Nuree Um ,  Ilgoo Youn ,  Jieun Lee ,  Donghyeon Jang ,  Seunghan Jo

IPC: H01L27/32

Abstract: A display panel may include a substrate, pixels, dummy pixels, and voltage lines. The substrate may include a first transmission region for light transmission and/or sound transmission, a non-display area surrounding the first transmission region, and a display area surrounding the non-display area. The pixels may be arranged on the display area and may emit light. The dummy pixels may be arranged on the non-display area, may include a first dummy pixel, and may emit no light. The voltage lines may transmit voltages to the pixels and the dummy pixels. The voltage lines may include a first voltage line and a second voltage line. The first voltage line may be spaced from the second voltage line, may be aligned with the second voltage line, and may overlap the first dummy pixel. The first transmission region may be positioned between the first voltage line and the second voltage line.

公开(公告)号：US20170154590A1

公开(公告)日：2017-06-01

申请号：US15229798

申请日：2016-08-05

Applicant: Samsung Display Co., Ltd.

Inventor： Sihyun Ahn ,  Yanghee Kim ,  Jaewon Kim ,  Seungsoo Baek

IPC: G09G3/36

CPC classification number: G09G3/3655 ,  G09G3/3659 ,  G09G3/3677 ,  G09G2300/043 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/02

Abstract: A gate driving circuit includes a plurality of driving stages configured to output a plurality of gates signals, a k-th driving stage (where k is a natural number greater than 2) being configured to receive a clock signal, a (k−1)-th carry signal from a (k−1)-th driving stage, a (k+1)-th carry signal from a (k+1)-th driving stage, a (k+2)-th carry signal from a (k+2)-th driving stage, a first ground voltage, a second ground voltage, and a third ground voltage, and to output a k-th gate signal and a k-th carry signal, and wherein the k-th driving stage comprises a first pull-down circuit configured to discharge the k-th gate signal to the third ground voltage in response to the (k+1)-th carry signal, wherein the third ground voltage changes within a range during a single frame section in which the plurality of driving stages sequentially outputs the plurality of gate signals.