公开(公告)号：US20160085627A1

公开(公告)日：2016-03-24

申请号：US14842356

申请日：2015-09-01

申请人： Kabushiki Kaisha Toshiba

发明人： Takao MARUKAME ,  Yoshifumi NISHI ,  Yusuke HIGASHI ,  Jiezhi CHEN ,  Kazuya MATSUZAWA ,  Yuichiro MITANI

IPC分类号： G06F11/10 ,  H03M13/00

CPC分类号： G06F11/1076 ,  H03M13/1102 ,  H03M13/152 ,  H03M13/2906 ,  H03M13/353 ,  H03M13/6516

摘要： According to an embodiment, a memory system includes a memory and a computation unit. Into the memory, data are written. The memory stores therein multiple check matrices. Each of the check matrices is associated with the number of errors in the written data. The computation unit is configured to perform a first error correction on the written data by selectively using, from among the check matrices, a check matrix associated with the number of errors recognized in the written data.

摘要翻译： 根据实施例，存储器系统包括存储器和计算单元。 进入内存，写入数据。 存储器中存储有多个校验矩阵。 每个校验矩阵与写入数据中的错误数量相关联。 计算单元被配置为通过从校验矩阵中选择性地使用与写入数据中识别的错误数量相关联的校验矩阵来对写入的数据执行第一纠错。