公开(公告)号：US20190220739A1

公开(公告)日：2019-07-18

申请号：US16225729

申请日：2018-12-19

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Young-Su KWON ,  Hyun Mi KIM ,  Jeongmin YANG

IPC: G06N3/08 ,  G06F7/523

CPC classification number: G06N3/08 ,  G06F7/523

Abstract: Provided is a neural network computing device including a neural network memory configured to store input data, a kernel memory configured to store kernel data corresponding to the input data, a kernel data controller configured to determine whether or not a first part of the kernel data matches a predetermined bit string, and if the first part matches the predetermined bit string, configured to generate a plurality of specific data based on a second part of the kernel data, and a neural core configured to perform a first operation between one of the plurality of specific data and the input data.

公开(公告)号：US20160283315A1

公开(公告)日：2016-09-29

申请号：US15008188

申请日：2016-01-27

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Young-Su KWON

IPC: G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/0721

Abstract: An apparatus and method for recovering the functionality of central processing unit core are disclosed herein. The apparatus for recovering the functionality of a central processing unit (CPU) core includes a functionality recovery buffer and a functionality recovery module unit. The functionality recovery buffer temporarily stores a value, to be stored in a register storage unit, in response to a write operation. The functionality recovery module unit performs the recovery of functionality by controlling the functionality recovery buffer when receiving a signal, indicating that a failure has been detected, from the outside.

Abstract translation: 本文公开了一种用于恢复中央处理单元核心的功能的装置和方法。 用于恢复中央处理单元（CPU）核心的功能的装置包括功能恢复缓冲器和功能恢复模块单元。 功能恢复缓冲器响应于写入操作临时存储要存储在寄存器存储单元中的值。 功能恢复模块单元通过在从外部接收到指示已经检测到故障的信号时控制功能恢复缓冲器来执行功能的恢复。

公开(公告)号：US20160110250A1

公开(公告)日：2016-04-21

申请号：US14858448

申请日：2015-09-18

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jin-Ho HAN ,  Young-Su KWON

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1064 ,  G06F12/0895 ,  G06F2212/1032

Abstract: The exemplary embodiments of the invention relates to fault tolerance of a cache memory which recovers an error occurred in the cache memory or reports an error. A cache memory may include a first layer cache configured to store data requested from a processor, together with a tag related to the data and parity check bits for detecting data error and tag error; a second layer cache configured to store data requested from the first layer cache, together with parity check bits and an error correction code(ECC) bit for detecting data error and tag error; and a fault tolerance unit configured to generate an error signal indicating whether the data error or tag error occurred in at least one of the first layer cache and the second layer cache is recoverable.

Abstract translation: 本发明的示例性实施例涉及高速缓冲存储器的容错，其恢复在高速缓冲存储器中发生的错误或报告错误。 高速缓冲存储器可以包括配置成存储从处理器请求的数据的第一层缓存以及与数据有关的标签和用于检测数据错误和标签错误的奇偶校验位; 第二层缓存，配置为存储从第一层高速缓存请求的数据，以及奇偶校验位和用于检测数据错误和标签错误的纠错码（ECC）位; 以及容错单元，被配置为生成指示在所述第一层高速缓冲存储器和所述第二层高速缓冲存储器中的至少一个中发生的数据错误或标签错误是否可恢复的错误信号。

公开(公告)号：US20160019126A1

公开(公告)日：2016-01-21

申请号：US14749558

申请日：2015-06-24

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Young-Su KWON

IPC: G06F11/20

CPC classification number: G06F11/1641 ,  G06F11/1438 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/1695 ,  G06F11/183

Abstract: Exemplary embodiments of the present invention relate to a failure recovery apparatus of digital logic circuit and method thereof when a fault occurs in the digital logic circuit. A failure recovery apparatus according to an embodiment of the present invention comprises: a fault detection block configured to determine fault occurrence by comparing output results of a plurality of digital logic circuit which perform the same operation using a clock having a first cycle; and a failure recovery block configured to perform a failure recovery operation of the plurality of digital logic circuit by using a clock having a second cycle which is longer than the first cycle when it is determined as that a fault occurs. According to exemplary embodiments of the present invention, when a fault occurs in digital logic circuits due to external factors, it provides high reliability in failure recovery of the digital logic circuits.

Abstract translation: 本发明的示例性实施例涉及数字逻辑电路的故障恢复装置及其在数字逻辑电路中发生故障时的方法。 根据本发明实施例的故障恢复装置包括：故障检测块，被配置为通过比较使用具有第一周期的时钟执行相同操作的多个数字逻辑电路的输出结果来确定故障发生; 以及故障恢复块，被配置为当确定为故障发生时，通过使用具有比所述第一周期长的第二周期的时钟来执行所述多个数字逻辑电路的故障恢复操作。 根据本发明的示例性实施例，当由于外部因素在数字逻辑电路中发生故障时，其在数字逻辑电路的故障恢复中提供高可靠性。

公开(公告)号：US20140359316A1

公开(公告)日：2014-12-04

申请号：US14256402

申请日：2014-04-18

Applicant: Electronics and Telecommunications Research Institute

Inventor： Young-Su KWON

IPC: G06F1/26

CPC classification number: G06F1/3243 ,  G06F1/30 ,  Y02D10/152

Abstract: A method and an apparatus for controlling an operation voltage of a processor core and a processor system including the same are provided. The apparatus for controlling an operation voltage of a processor core includes a voltage supplier and an operation voltage searching core. The voltage supplier supplies the operation voltage to the processor core. The operation voltage searching core requests the processor core to execute a program, and controls the operation voltage based on whether the program has been normally operated.

Abstract translation: 提供了一种用于控制处理器核心和包括该处理器核心的处理器系统的操作电压的方法和装置。 用于控制处理器核心的操作电压的装置包括电压供应器和操作电压搜索核心。 电压供应器将操作电压提供给处理器内核。 操作电压搜索核心请求处理器核心执行程序，并且基于程序是否正常工作来控制操作电压。