Adaptive timeout mechanism
    41.
    发明授权

    公开(公告)号:US10592322B1

    公开(公告)日:2020-03-17

    申请号:US15634696

    申请日:2017-06-27

    Abstract: Disclosed herein are techniques for preventing or minimizing completion timeout errors on a computer device. An apparatus includes a processing logic circuit configured to perform transactions requested by a requester device, and a timeout prevention logic coupled to the processing logic circuit. The timeout prevention logic includes a timeout logic and a moderation logic. The timeout logic is configured to, when the processing logic circuit fails to complete a particular transaction requested by the requester device within a reconfigurable time period, generate a timeout event and complete the particular requested transaction. The moderation logic is configured to determine a number of timeout events generated by the timeout logic during a monitoring time period, and set the reconfigurable time period based on the number of timeout events generated by the timeout logic during the monitoring time period.

    ACCELERATED QUANTIZED MULTIPLY-AND-ADD OPERATIONS

    公开(公告)号:US20190294413A1

    公开(公告)日:2019-09-26

    申请号:US15934681

    申请日:2018-03-23

    Abstract: Disclosed herein are techniques for accelerating convolution operations or other matrix multiplications in applications such as neural network. A computer-implemented method includes receiving low-precision inputs for a convolution operation from a storage device, and subtracting a low-precision value representing a high-precision zero value from the low-precision inputs to generate difference values, where the low-precision inputs are asymmetrically quantized from high-precision inputs. The method also includes performing multiplication and summation operations on the difference values to generate a sum of products, and generating a high-precision output by scaling the sum of products with a scaling factor.

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