公开(公告)号：US06611181B2

公开(公告)日：2003-08-26

申请号：US09797631

申请日：2001-03-01

申请人： Nandu J. Marketkar ,  John R. Benham ,  Thomas F. Knight, Jr. ,  Rajeevan Amirtharajah

发明人： Nandu J. Marketkar ,  John R. Benham ,  Thomas F. Knight, Jr. ,  Rajeevan Amirtharajah

IPC分类号： H01P500

CPC分类号： H01P5/185 ,  H01P5/187 ,  H05K1/0228 ,  H05K1/0237 ,  H05K1/0239 ,  H05K1/0245 ,  H05K1/14 ,  H05K2201/09263 ,  H05K2201/097

摘要： An electromagnetic (EM) coupler including a first transmission structure having a first geometry, and a second transmission structure having a second geometry and forming an EM coupler with the first transmission structure, the first and second geometries being selected to reduce sensitivity of EM coupling to relative positions of the first and second transmission structures is disclosed.

摘要翻译： 一种包括具有第一几何形状的第一传输结构和具有第二几何形状并形成具有第一传输结构的EM耦合器的第二传输结构的电磁（EM）耦合器，选择第一和第二几何形状以降低EM耦合到 公开了第一和第二传输结构的相对位置。

公开(公告)号：US06496918B1

公开(公告)日：2002-12-17

申请号：US09892812

申请日：2001-06-27

申请人： André DeHon ,  Ethan Mirsky ,  Thomas F. Knight, Jr.

发明人： André DeHon ,  Ethan Mirsky ,  Thomas F. Knight, Jr.

IPC分类号： G06F900

CPC分类号： G06F15/8023

摘要： A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources, such as memory and processing, are deployable in a way that takes advantage of the opportunities for optimization present in given problems. To accomplish this, the interconnect supports three different modes of operation: a static value in which a value set by the configuration data is provided to a functional unit, static source in which another functional unit serves as the value source, and a dynamic source mode in which the source is determined by the value from another functional unit.

摘要翻译： 可编程集成电路利用大量的中间粒度处理元件，它们是以可配置的网格布置的多位处理单元。 诸如内存和处理之类的粗粮资源可以利用在给定问题中存在的优化机会的方式进行部署。 为了实现这一点，互连支持三种不同的操作模式：将由配置数据设置的值提供给功能单元的静态值，其他功能单元用作值源的静态源，以及动态源模式 其中源由另一功能单元的值确定。

公开(公告)号：US06456339B1

公开(公告)日：2002-09-24

申请号：US09181320

申请日：1998-10-28

申请人： Rajeev J. Surati ,  Thomas F. Knight, Jr.

发明人： Rajeev J. Surati ,  Thomas F. Knight, Jr.

IPC分类号： H04N322

CPC分类号： G03B37/04 ,  H04N9/12 ,  H04N9/3147 ,  H04N9/3194

摘要： A super-resolution display derives a map by selectively driving the display while sensing the display output. A stored pixel correction function based on the mapping is applied to pixel data corresponding to the images to be displayed, and the display is driven from the corrected or modified pixel data. This can be used to correct for many types of distortion and to blend images from plural projectors. Pixel data is stored in a frame buffer, and the pixel correction function is applied to the pixel data between the frame buffer and the display, or alternatively, the pixel correction function is applied first, and corrected pixel data is stored in the frame buffer. The display is then driven from the corrected pixel data. In a preferred embodiment, the display comprises a plurality of projectors. The pixel correction function corrects for misalignment of projected overlapping pixel arrays, and blends the overlapping projection regions. In another embodiment, the projected images from plural projectors completely overlap, and the projectors have a small fill factor, resulting in a super-high resolution display. A single projector embodiment corrects for imperfections across the display. The correction functions are derived by composing a screen to sensor mapping with projector to sensor mappings. These mappings are established by optically sensing physical or projected test charts. Preferably, the optical sensor comprises at least one camera, such as a CCD camera. Alternatively, the optical sensor may comprise a pair of orthogonal linear sensor arrays.

摘要翻译： 超分辨率显示器通过在感测显示输出的同时选择性地驱动显示器来导出地图。 基于映射的存储像素校正功能被应用于与要显示的图像相对应的像素数据，并且从校正或修改的像素数据驱动显示。 这可以用于纠正许多类型的失真并混合多个投影机的图像。 像素数据被存储在帧缓冲器中，并且像素校正功能被应用于帧缓冲器和显示器之间的像素数据，或者，首先应用像素校正功能，并且校正的像素数据被存储在帧缓冲器中。 然后从校正的像素数据驱动显示。 在优选实施例中，显示器包括多个投影仪。 像素校正功能校正投影的重叠像素阵列的未对准，并且混合重叠投影区域。 在另一个实施例中，来自多个投影仪的投影图像完全重叠，并且投影仪具有小的填充因子，导致超高分辨率显示。 单个投影机实施例校正了整个显示器上的缺陷。 校正功能是通过将投影仪与传感器映射的屏幕组合成传感器映射得出的。 这些映射是通过光学感测物理或投影测试图建立的。 优选地，光学传感器包括至少一个照相机，例如CCD照相机。 或者，光学传感器可以包括一对正交的线性传感器阵列。

公开(公告)号：US4709327A

公开(公告)日：1987-11-24

申请号：US499471

申请日：1983-05-31

申请人： W. Daniel Hillis ,  Thomas F. Knight, Jr. ,  Alan Bawden ,  Brewster L. Kahle ,  David Chapman ,  David P. Christman ,  Cliff A. Lasser ,  Carl R. Feynman

发明人： W. Daniel Hillis ,  Thomas F. Knight, Jr. ,  Alan Bawden ,  Brewster L. Kahle ,  David Chapman ,  David P. Christman ,  Cliff A. Lasser ,  Carl R. Feynman

IPC分类号： G06F15/80 ,  G06F15/16

CPC分类号： G06F15/8023

摘要： A parallel processing circuit is disclosed for use as the processor/memory in a highly parallel processor. The circuit comprises an instruction decoder that generates tables of outputs in response to instructions received at the decoder and a plurality of processor/memories each of which comprises a read/write memory and a processor for producing an output depending at least in part on data read from the memory and instruction information received at the instruction decoder. In addition, the circuit provides means for simultaneously addressing at least one cell in each read/write memory to write data thereto or read data therefrom and means for providing to each processor an output table from the decoder, the particular output table depending on instruction information received at the decoder. Further the processing circuit comprises means for selecting from the output table a particular output depending on data input to the processor. Advantageously, each processor/memory also comprises a flag controller for controlling the reading of a plurality of flags and means for simultaneously addressing each flag controller to read a flag for input into the processor associated therewith.Preferably, each processor is a bit-serial processor with three inputs, two from the read/write memory and one from the flag controller, and two outputs, one to the read/write memory and one to the flag controller; and the decoder and the plurality of processor/memories and formed on a single, integrated circuit chip.

摘要翻译： 公开了一种用于高度并行处理器中的处理器/存储器的并行处理电路。 电路包括指令解码器，其响应于在解码器处接收到的指令而生成输出表，以及多个处理器/存储器，每个处理器/存储器包括读/写存储器和用于至少部分地基于数据读取产生输出的处理器 从在指令解码器处接收的存储器和指令信息。 此外，电路提供用于同时寻址每个读/写存储器中的至少一个单元以向其中写入数据或从其读取数据的装置，用于向每个处理器提供来自解码器的输出表的装置，该特定输出表取决于指令信息 在解码器处接收。 此外，处理电路包括用于根据输入到处理器的数据从输出表选择特定输出的装置。 有利地，每个处理器/存储器还包括用于控制多个标志的读取的标志控制器和用于同时寻址每个标志控制器以读取用于输入到与其相关联的处理器的标志的装置。 优选地，每个处理器是具有三个输入的位串行处理器，两个来自读/写存储器和一个来自标志控制器的两个输出，一个输出到读/写存储器，一个输出到该标志控制器; 以及解码器和多个处理器/存储器并形成在单个集成电路芯片上。