Generic encoder for low-density parity-check (LDPC) codes

    公开(公告)号:US10372530B1

    公开(公告)日:2019-08-06

    申请号:US15606720

    申请日:2017-05-26

    摘要: Systems and methods are provided for encoding data based on an LDPC code using various inversion mechanisms to obtain parity bits. In some embodiments, an LDPC encoder may compute parity bits using a speculative recursion and correction mechanism. In these embodiments, the LDPC encoder may initiate a recursion using at least one speculative value in place of the actual value for a parity component. The speculative values may then be corrected using a correction factor. In other embodiments, an LDPC encoder is provided that can perform a blockwise inversion mechanism. This mechanism may be used on LDPC codes with parity check matrices having a parity portion composed partially of a large triangular matrix. In still other embodiments, a generic LDPC encoder is provided. The generic LDPC encoder can implement a variety of different encoding techniques, such as different inversion mechanisms, and may be processor-based or finite state machine-based.

    Multi-channel RF system with off-channel scanning

    公开(公告)号:US10368303B1

    公开(公告)日:2019-07-30

    申请号:US15868526

    申请日:2018-01-11

    IPC分类号: H04W48/16 H04W84/12

    摘要: A radiofrequency system includes a plurality of transceivers providing a plurality of channels, and circuitry configured to perform off-channel functions. A first subset of channels performs radiofrequency communication functions, and a second subset of channels provides signals for the off-channel functions. The first subset of channels may be provided by a first subset of transceivers, and the second subset of channels may be provided by a second subset of transceivers. A spectrum sensing unit may select between the first subset of transceivers and the second subset of transceivers. The circuitry configured to perform the off-channel functions may use the second subset of the plurality of channels to perform neighborhood discovery. The circuitry configured to perform the off-channel functions may scan available communications channels for interference, storing identifications of interference-free channels, and, upon detection of interference on a channel in use, may select one of the interference-free channels.

    System and method for providing communication coexistence among different radio technologies via synchronization and time slot allocation

    公开(公告)号:US10349364B1

    公开(公告)日:2019-07-09

    申请号:US15013002

    申请日:2016-02-02

    发明人: Paul A. Lambert

    IPC分类号: H04W56/00 H04W72/04 H04W84/12

    摘要: Apparatus, methods, and other embodiments associated with the coexistence of multiple radio devices in a same environment are described. According to one embodiment, a non-transitory computer-readable medium storing computer-executable instructions includes instructions for transmitting and receiving radio signals in accordance with at least one wireless communication technology. The instructions also include instructions for discovering a plurality of radio devices operating within a same radio band within a same geographic region. At least one radio device of the plurality of radio devices operates based on at least two different wireless communication technologies. The instructions further include instructions for generating a master clock reference and temporally synchronizing the plurality of radio devices with respect to the master clock reference.

    Method and apparatus for retransmission

    公开(公告)号:US10306704B1

    公开(公告)日:2019-05-28

    申请号:US15589774

    申请日:2017-05-08

    摘要: Aspects of the disclosure provide an apparatus for wireless communication. The apparatus includes a transceiver and a processing circuit. The transceiver is configured to transmit and receive wireless signals. The processing circuit is configured to detect an error of a previous scheduled transmission of data units from the apparatus to another apparatus. The other apparatus provides scheduled resources for transmission between the two apparatuses. Further, the processing circuit is configured to determine resources that are scheduled by the other apparatus for the apparatus to perform retransmission, and provide one or more of the data units in the previous scheduled transmission to the transceiver for retransmission using the scheduled resources.

    Method and apparatus for control frame extension

    公开(公告)号:US10257328B2

    公开(公告)日:2019-04-09

    申请号:US15691398

    申请日:2017-08-30

    IPC分类号: H04L29/06 H04W84/12

    摘要: Aspects of the disclosure provide an apparatus having a processing circuit and a transceiver. The processing circuit is configured to generate a frame to have an extended subtype under a control type, configure a media access control (MAC) header of the frame to indicate an extended control frame format, and configure a field of the frame to be an extended subtype field according to the extended control frame format to carry an identification for the extended subtype. The extended subtype is defined in addition to a plurality of subtypes that are identifiable using a subtype field in the frame according to a control frame format. The transceiver is configured to transmit signals to carry the frame.

    Sub-carrier adaptation in multi-carrier communication systems

    公开(公告)号:US10212019B1

    公开(公告)日:2019-02-19

    申请号:US16113972

    申请日:2018-08-27

    摘要: A communication device determines an estimate of a communication channel, and determines, based on the estimate of the communication channel, a plurality of pairs of modulation schemes and encoding schemes to be used for a packet, including: i) determining, for a first set of adjacent orthogonal frequency division multiplexing (OFDM) subcarriers, a first pair of a modulation scheme and an encoding scheme; and ii) determining, for a second set of adjacent OFDM subcarriers, a second pair of a modulation scheme and an encoding scheme, the second pair being different than the first pair. The communication device generates the packet for transmission, wherein i) all data modulated on the first set of adjacent OFDM subcarriers is modulated and encoded using the first pair, and ii) all data modulated on the second set of adjacent OFDM subcarriers is modulated and encoded using the second pair.

    Systems and methods for operating a brushless DC motor

    公开(公告)号:US10193476B1

    公开(公告)日:2019-01-29

    申请号:US15386491

    申请日:2016-12-21

    IPC分类号: H02P6/28

    摘要: A system for controlling operation of a brushless DC motor is provided. The system includes a memory, driving profile and motor controllers, and an inverter. The memory stores: a scaling factor indicative of how much to increase an operating parameter of a base driving profile; and the base driving profile indicative of speed over time of a drive cycle of the brushless DC motor. The driving profile controller generates a motor driving profile, indicating an operating parameter for driving the brushless DC motor, where the operating parameter is based on (i) the scaling factor, and (ii) the base driving profile. The controller generates a control signal based on the operating parameter of the motor driving profile. The inverter: receives a direct current from a DC source; responsively to the control signal, converts the direct current to an alternating current; and drives the brushless DC motor via the alternating current.

    Systems and methods for gray coding based error correction in an asynchronous counter

    公开(公告)号:US10187082B1

    公开(公告)日:2019-01-22

    申请号:US15812797

    申请日:2017-11-14

    IPC分类号: H03M7/16 H03M13/03 H03K23/00

    摘要: Embodiments described herein provide a method for correcting a propagation delay induced error in an output of an asynchronous counter. An input clock is applied to the asynchronous counter. A gray-code count is generated by the asynchronous counter. The gray-code count is mapped to a binary count. An error component, indicative of a counting error induced by a propagation delay between the input clock and the binary count, is generated by taking an exclusive-OR operation over the gray-code count and the input clock. The error component is added to the binary count to generate an error-corrected binary count. The error-corrected binary count is output.