公开(公告)号：US07906399B2

公开(公告)日：2011-03-15

申请号：US12416042

申请日：2009-03-31

申请人： Jung Ho Ahn

发明人： Jung Ho Ahn

IPC分类号： H01L21/336

CPC分类号： H01L29/41758 ,  H01L29/78

摘要： Disclosed is a semiconductor transistor for enhancing performance of PMOS and NMOS transistors, particularly current driving performance, while reducing a narrow width effect. A narrow width MOS transistor includes: a channel of which width is W0 and length is L0; an active area including source and drain areas formed at both sides with the channel as a center; a gate insulating layer formed on the channel; a gate conductor formed on the gate insulating layer and intersecting the active area; a first additional active area of width is larger than that W0 of the channel as an active area added to the source area; and a second additional active area of width is larger than that W0 of the channel as an active area added to the drain area. When the structure of the transistor having the additional active areas is applied to NMOS and PMOS transistors, a driving current is represented as 107.27% and 103.31%, respectively. Accordingly, the driving currents of both PMOS and NMOS transistors are enhanced.

摘要翻译： 公开了一种用于增强PMOS和NMOS晶体管的性能的半导体晶体管，特别是电流驱动性能，同时减小窄宽度效应。 窄宽度的MOS晶体管包括：宽度为W0且长度为L0的沟道; 一个有效区域，包括以通道为中心形成在两侧的源区和漏区; 形成在所述通道上的栅极绝缘层; 栅极导体，形成在栅极绝缘层上并与有源区相交; 宽度的第一附加有效区域大于作为添加到源区域的活动区域的信道的W0; 并且宽度的第二附加有源区域大于作为添加到漏极区域的有源区域的沟道的W0。 当具有附加有源区的晶体管的结构被施加到NMOS和PMOS晶体管时，驱动电流分别表示为107.27％和103.31％。 因此，增加了PMOS和NMOS晶体管的驱动电流。

公开(公告)号：US20090057782A1

公开(公告)日：2009-03-05

申请号：US12189168

申请日：2008-08-10

申请人： Jung-Ho Ahn

发明人： Jung-Ho Ahn

IPC分类号： H01L29/78

CPC分类号： H01L29/41758 ,  H01L29/4238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is disclosed. Embodiments relate to a semiconductor device which includes an active region including a source region, a drain region, and a channel region. A gate electrode, source electrodes, and a drain electrode are formed around the active region. A plurality of gate fingers diverge from the gate electrode into the channel region. A plurality of source fingers diverge from the source electrodes into the source region, the source fingers being disposed between the gate fingers in a predetermined pattern, the source fingers having at least two finger lines connected to each other via at least one grid line. A plurality of drain fingers diverge from the drain electrode into the drain region, the drain fingers being disposed between the gate fingers where the source fingers are not disposed.

摘要翻译： 公开了一种半导体器件。 实施例涉及包括有源区域的半导体器件，该有源区域包括源极区域，漏极区域和沟道区域。 在有源区域周围形成栅电极，源极和漏电极。 多个栅极指从栅电极发散到沟道区。 多个源极指状物从源电极发散到源极区域中，源极指状物以预定图案设置在栅极指状物之间，源极指具有经由至少一个栅格线彼此连接的至少两根指状线。 多个漏极指从漏极扩散到漏极区域中，漏极指配置在没有设置源极指的栅极指之间。

公开(公告)号：US20080157218A1

公开(公告)日：2008-07-03

申请号：US11957255

申请日：2007-12-14

申请人： Jung-Ho Ahn

发明人： Jung-Ho Ahn

IPC分类号： H01L23/532 ,  H01L29/49 ,  H01L21/336 ,  H03K17/687

CPC分类号： H01L27/092 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/665 ,  H01L29/7833 ,  H01L2924/0002 ,  H03K17/687 ,  H03K17/6871 ,  H03K2017/6878 ,  H01L2924/00

摘要： A semiconductor device including a semiconductor substrate having source/drain regions, a gate electrode formed on and/or over the semiconductor substrate, spacers formed against sidewalls of the gate electrode, an interlayer insulating layer formed over the semiconductor substrate and the gate electrode and having a plurality of contact holes formed therein, and contact plugs formed within the contact holes. The contact plugs can include a first contact plug and a second contact plug electrically connected to the gate electrode, and a third contact plug and a fourth contact plug electrically connected to the source/drain regions.

摘要翻译： 一种半导体器件，包括具有源极/漏极区域的半导体衬底，形成在半导体衬底上和/或之上的栅电极，形成在栅电极的侧壁上的间隔物，形成在半导体衬底和栅电极上的层间绝缘层， 形成在其中的多个接触孔和形成在接触孔内的接触塞。 接触插塞可以包括电连接到栅电极的第一接触插塞和第二接触插塞，以及电连接到源极/漏极区域的第三接触插塞和第四接触插塞。

公开(公告)号：US20070152241A1

公开(公告)日：2007-07-05

申请号：US11612586

申请日：2006-12-19

申请人： Jung Ho Ahn

发明人： Jung Ho Ahn

IPC分类号： H01L27/10

CPC分类号： H01L27/0805 ,  H01L27/0629 ,  H01L27/0811 ,  H01L28/40

摘要： A gate capacitor having a horizontal structure and a method for manufacturing the same is provided. The gate capacitor having a horizontal structure can be formed on a semiconductor substrate and used as a MOS transistor. The gate capacitor includes at least two adjacent gate electrodes and a capacitor dielectric layer filled between the two gate electrodes. In this case, insulating spacers can be formed at a sidewall of the gate electrodes in which the capacitor dielectric layer is not formed. As the gate capacitors can be used as a MOS transistor, a gate insulating layer can be formed between the two gate electrodes and the semiconductor substrate.

摘要翻译： 提供一种具有水平结构的栅极电容器及其制造方法。 具有水平结构的栅极电容器可以形成在半导体衬底上并用作MOS晶体管。 栅极电容器包括至少两个相邻的栅电极和填充在两个栅电极之间的电容器电介质层。 在这种情况下，可以在不形成电容器电介质层的栅电极的侧壁处形成绝缘间隔物。 由于栅极电容器可以用作MOS晶体管，所以可以在两个栅电极和半导体衬底之间形成栅极绝缘层。