SIGNAL BRIDGING USING AN UNPOPULATED PROCESSOR INTERCONNECT

    公开(公告)号:US20230297533A1

    公开(公告)日:2023-09-21

    申请号:US18322183

    申请日:2023-05-23

    发明人: JASON R. TALBERT

    IPC分类号: G06F13/40 G06F13/20

    摘要: Signal bridging using an unpopulated processor interconnect, including: communicatively coupling an apparatus to a plurality of first signal paths between a bootstrap processor (BSP) and a processor interconnect of a circuit board; communicatively coupling the apparatus to a plurality of second signal paths between the processor interconnect and a peripheral interface of the circuit board; and communicatively coupling the BSP to the peripheral interface via one or more third signal paths in the apparatus.

    System, method, and non-transitory computer readable medium for detecting baseboard management controller

    公开(公告)号:US11762791B1

    公开(公告)日:2023-09-19

    申请号:US17856082

    申请日:2022-07-01

    发明人: Li-Yun Hao

    IPC分类号: G06F13/20

    CPC分类号: G06F13/20 G06F2213/40

    摘要: A system and a method for detecting baseboard management controller (BMC) includes the BMC and a CPLD. The BMC includes a GPIO and configured to drive the GPIO to output a first signal. The CPLD is connected to the GPIO and is configured to determine a status of the BMC by detecting whether the GPIO outputs the first signal. When the CPLD detects that the GPIO is not outputting the first signal, the CPLD determines that the BMC is in an abnormal status; when the CPLD detects that the GPIO is outputting the first signal and a level status of the first signal is switched in a predetermined time, the CPLD determines that the BMC is in a normal status.

    System to use descriptor rings for I/O communication

    公开(公告)号:US11741029B2

    公开(公告)日:2023-08-29

    申请号:US17894116

    申请日:2022-08-23

    申请人: Red Hat, Inc.

    发明人: Michael Tsirkin

    IPC分类号: G06F13/20 G06F9/455 G06F13/42

    摘要: A system and method for input/output communication is disclosed. In one embodiment, a device identifies a queue including a plurality of input/output (I/O) descriptors, each of the plurality of I/O descriptors representing one of: an active descriptor associated with an active I/O request or an executed descriptor that is associated with an executed I/O request. The device retrieves, from a first index in the queue, one or more active descriptors associated with an I/O request. The device executes the I/O request. The device writes a first executed descriptor to a second index in the queue, where the first executed descriptor indicates the I/O request has been executed.

    Peeking and polling storage management system and method

    公开(公告)号:US11726820B2

    公开(公告)日:2023-08-15

    申请号:US16402637

    申请日:2019-05-03

    IPC分类号: G06F9/46 G06F9/48 G06F13/20

    CPC分类号: G06F9/4887 G06F13/20

    摘要: A method, computer program product, and computing system for defining an affined OS-thread on each core of a multicore microprocessor, thus defining a plurality of affined OS-threads; executing a sequentially-activated polling thread on each of the affined OS-threads, wherein the sequentially-activated polling thread is configured to detect waiting IO activity on IO interfaces associated with the affined OS-threads; and if waiting IO activity is detected, activating one or more X-threads on a specific affined OS-thread that is associated with a specific IO interface on which the waiting IO activity was detected.

    HYBRID ASYNCHRONOUS NETWORK-ON-CHIP OPTIMIZED FOR ARTIFICIAL INTELLIGENCE WORKLOADS

    公开(公告)号:US20230251983A1

    公开(公告)日:2023-08-10

    申请号:US18106476

    申请日:2023-02-06

    申请人: Chronos Tech LLC

    IPC分类号: G06F13/20

    CPC分类号: G06F13/20 G06F2213/40

    摘要: A hybrid asynchronous network-on-chip (NoC) optimized for artificial intelligence workloads utilizes a “tile” layout methodology with a plurality of tiles, each tile including an asynchronous node with a plurality of input ports and output ports for communicating with adjacent asynchronous nodes on adjacent tiles, along with a processor input port and processor output port configured to transport data from an asynchronous processor, but capable of being customized to transport data between a synchronous processor through the implementation of modular synchronous-to-asynchronous and asynchronous-to-synchronous first-in-first-out (FIFO) buffers. The asynchronous NoC is able to efficiently satisfy the interconnect traffic requirement of modern machine learning systems, eliminating the need for a global clock distribution and enabling unlimited scalability while providing high throughput and minimal latency performance.

    Adapter device and communication method

    公开(公告)号:US11709788B2

    公开(公告)日:2023-07-25

    申请号:US17186530

    申请日:2021-02-26

    摘要: An adapter device communicates with a sink device and a source device using first and second communication schemes, respectively. The adapter device includes: a transceiver receiving a state read request by detecting that a serial data line connected between the adapter device and the sink device is driven to a low level when a serial clock line connected therebetween is at a high level, and drive the serial data line to the low level and drive the serial clock line to a low level; a transmitter transmitting the state read request to the source device after the serial clock line is driven to the low level; and a receiver receiving a state read signal to read data of a state register in the sink device from the source device, wherein the transceiver transmits the state read signal to the sink device via the serial data line.