公开(公告)号：US10593638B2

公开(公告)日：2020-03-17

申请号：US15473294

申请日：2017-03-29

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Suresh Ramalingam ,  Henley Liu

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498

Abstract: Methods and apparatus are described for enabling copper-to-copper (Cu—Cu) bonding at reduced temperatures (e.g., at most 200° C.) by significantly reducing Cu oxide formation. These techniques provide for faster cycle time and entail no extraordinary measures (e.g., forming gas). Such techniques may also enable longer queue (Q) or staging times. One example semiconductor structure generally includes a semiconductor layer, an adhesion layer disposed above the semiconductor layer, an anodic metal layer disposed above the adhesion layer, and a cathodic metal layer disposed above the anodic metal layer. An oxidation potential of the anodic metal layer may be greater than an oxidation potential of the cathodic metal layer. Such a semiconductor structure may be utilized in fabricating IC packages implementing 2.5D or 3D integration.

公开(公告)号：US10529645B2

公开(公告)日：2020-01-07

申请号：US15617774

申请日：2017-06-08

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Henley Liu ,  Tien-Yu Lee ,  Gamal Refai-Ahmed ,  Myongseob Kim ,  Ferdinand F. Fernandez ,  Ivor G. Barber ,  Suresh Ramalingam

IPC: H01L23/367 ,  H01L23/10 ,  H01L23/055 ,  H01L25/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498

Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a lid with recessed areas in the inner surfaces of the lid. The recessed areas (e.g., trenches) provide receptacles for accepting a portion of a thermal interface material (TIM) that may be forced out when the lid is positioned on the TIM above one or more integrated circuit (IC) dies during fabrication of the IC package. In this manner, the TIM bond line thickness (BLT) between the lid and the IC die(s) may be reduced for decreased thermal resistance, but sufficient interfacial adhesion is provided for the IC package with such a lid to avoid TIM delamination.

公开(公告)号：US10527670B2

公开(公告)日：2020-01-07

申请号：US15471390

申请日：2017-03-28

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Ivor G. Barber ,  Suresh Ramalingam ,  Jaspreet Singh Gandhi ,  Tien-Yu Lee ,  Henley Liu ,  David M. Mahoney ,  Mohsen H. Mardi

IPC: G01R31/28

Abstract: Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a plurality of independently movable pushers. The plurality of pushers are configured to engage the IC package disposed the socket.

公开(公告)号：US10403591B2

公开(公告)日：2019-09-03

申请号：US15798748

申请日：2017-10-31

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi

IPC: H01L23/48 ,  H01L21/00 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a first substrate containing first circuitry, a first contact pad, a first pillar, a first pillar protection layer, a second substrate containing second circuitry, and a solder ball disposed on the first pillar and electrically and mechanically coupling the first substrate to the second substrate. The first contact pad is disposed on the first substrate and coupled to the first circuitry. The first pillar electrically disposed over the first contact pad. The first pillar protection layer is hydrophobic to solder and is disposed on a side surface of the first pillar.

公开(公告)号：US20190259695A1

公开(公告)日：2019-08-22

申请号：US15902949

申请日：2018-02-22

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Vadim Heyfitch

IPC: H01L23/498 ,  G01R31/317 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/64 ,  H01L21/48 ,  H01L21/56

Abstract: A chip package and method of fabricating the same are described herein. The chip package includes a high speed data transmission line that has an inter-die region through which a signal transmission line couples a first die to a second die. The signal transmission line has a resistance greater than an equivalent base resistance (EBR) of a copper line, which reduces oscillation within the transmission line.