公开(公告)号：US11658101B2

公开(公告)日：2023-05-23

申请号：US17219830

申请日：2021-03-31

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/34 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49568 ,  H01L21/4821 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/34 ,  H01L23/49513 ,  H01L23/49558 ,  H01L23/49586 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/48175

Abstract: In a described example, an apparatus includes: a package substrate having a die pad configured for mounting a semiconductor die, a first lead connected to the die pad, and a second lead spaced from and electrically isolated from the die pad; a spacer dielectric mounted on the die pad; a semiconductor die including a temperature sensor mounted on the spacer dielectric; electrical connections coupling the semiconductor die to the second lead; and mold compound covering the semiconductor die, the die pad, the electrical connections, and a portion of the package substrate, with portions of the first lead and portions of the second lead exposed from the mold compound to form terminals for a packaged temperature sensor device.

公开(公告)号：US20230097816A1

公开(公告)日：2023-03-30

申请号：US17491522

申请日：2021-09-30

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: H01L23/60 ,  H01L23/00

Abstract: In a described example, an apparatus includes: a semiconductor die having bond pads on a device side surface, the semiconductor die having a ground plane spaced from the bond pads by a spacing distance. The bond pads have an upper surface for receiving a ball bond, and an outer boundary, the bond pads having vertical sides extending from the upper surface to a bottom surface, the bottom surface formed over the device side surface of the semiconductor die. A protective overcoat (PO) is formed overlying the ground plane and overlying the vertical sides of the bond pads, and overlying a portion of the upper surface of the bond pads, and having an opening exposing the remaining portion of the upper surface of the bond pads, the protective overcoat having a dielectric constant of less than 3.8.

公开(公告)号：US11569396B2

公开(公告)日：2023-01-31

申请号：US17088963

申请日：2020-11-04

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: H01L31/0203 ,  H01L31/02 ,  G01J1/02 ,  H01L31/173

Abstract: An optical sensor package includes an IC die including a light sensor element, an output node, and bond pads including a bond pad coupled to the output node. A leadframe includes a plurality of leads or lead terminals, wherein at least some of the plurality of leads or lead terminals are coupled to the bond pads including to the bond pad coupled to the output node. A mold compound provides encapsulation for the optical sensor package including for the light sensor element. The mold compound includes a polymer-base material having filler particles including at least one of infrared or terahertz transparent particle composition provided in a sufficient concentration so that the mold compound is optically transparent for providing an optical transparency of at least 50% for a minimum mold thickness of 500 μm in a portion of at least one of an infrared frequency range and a terahertz frequency range.

公开(公告)号：US11557722B2

公开(公告)日：2023-01-17

申请号：US17142539

申请日：2021-01-06

Applicant: Texas Instruments Incorporated

Inventor： Ming Li ,  Yiqi Tang ,  Jie Chen ,  Enis Tuncer ,  Usman Mahmood Chaudhry ,  Tony Ray Larson ,  Rajen Manicon Murugan ,  John Paul Tellkamp ,  Satyendra Singh Chauhan

IPC: H01L43/14 ,  G01R33/07 ,  G01R15/20 ,  H01L43/06 ,  H01L23/495 ,  G01R33/00

Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including≥1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ≥1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.

公开(公告)号：US11552013B2

公开(公告)日：2023-01-10

申请号：US17218941

申请日：2021-03-31

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: H01L23/525 ,  H01L23/498 ,  H01L23/00

Abstract: In a described example, an apparatus includes: a package substrate having a die pad configured for mounting a semiconductor die, and leads spaced from the die pad; a semiconductor die mounted on the die pad; a fuse mounted to a lead, the fuse having a fuse element coupled between a fuse cap and the lead, the fuse having a fuse body with an opening surrounding the fuse element, the fuse cap attached to the fuse body; electrical connections coupling the semiconductor die to the fuse; and mold compound covering the semiconductor die, the fuse, the electrical connections, and a portion of the package substrate, with portions of the leads exposed from the mold compound to form terminals.

公开(公告)号：US11342251B2

公开(公告)日：2022-05-24

申请号：US17015059

申请日：2020-09-08

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: H01L23/495

Abstract: A microelectronic device includes a first conductor and a second conductor, separated by a lateral spacing. The first conductor has a low field contour facing the second conductor. The low field contour has offsets from a tangent line to the first conductor on the low field contour. Each of the offsets increases a separation of the high voltage conductor from the low voltage conductor. A first offset, located from an end of the high voltage conductor, at a first lateral distance of 25 percent of the minimum separation, is 19 percent to 28 percent of the minimum separation. A second offset, located at a second lateral distance of 50 percent of the minimum separation, is 9 percent to 14 percent of the minimum separation. A third offset, located at a third lateral distance of 75 percent of the minimum separation, is 4 percent to 6 percent of the minimum separation.

公开(公告)号：US11322433B2

公开(公告)日：2022-05-03

申请号：US16842567

申请日：2020-04-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Enis Tuncer ,  Alejandro Hernandez-Luna

IPC: H01L23/31 ,  H01L23/498 ,  H01L43/06

Abstract: In some examples, a package comprises first and second terminals and a conductive pathway coupling the first and second terminals. The conductive pathway is configured to generate a magnetic field. The package comprises a conductive member aligned with and coupled to the conductive pathway. The conductive pathway and the conductive member have a common shape. The package also comprises an insulative layer coupled to the conductive member and a die coupled to the insulative layer and having a circuit configured to measure the magnetic field. The circuit faces the conductive pathway.

公开(公告)号：US20210287970A1

公开(公告)日：2021-09-16

申请号：US16819902

申请日：2020-03-16

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer ,  John Paul Tellkamp

IPC: H01L23/495 ,  H01L43/04 ,  H01L21/48

Abstract: A leadframe includes leads or lead terminals, a plurality of folded features including i) support features positioned within an area defined in at least one dimension by the leads or the lead terminals configured for supporting at least one of a die pad and a first pad and a second pad spaced apart from one another, or ii) current carrying features. At least one of the folded features includes a planar portion and a folded edge structure that curves upwards at an angle of at least 45° relative to the planar portion. The folded features are configured to provide an effective increase in thickness to reduce the deformation observed in assembly.

公开(公告)号：US10998256B2

公开(公告)日：2021-05-04

申请号：US16533566

申请日：2019-08-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Enis Tuncer

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

Abstract: An apparatus includes a first die attach pad and a second die attach pad. A first die is attached to the first die attach pad and a second die is attached to the second die attach pad. The first die attach pad and the second die attach pad are separated by a gap. A first edge of the first die attach pad adjacent to the gap is thinner than a second edge of the first die attach pad. The first edge of the first die attach pad is opposite the second edge of the first die attach pad. A first edge of the second die attach pad adjacent to the gap is thinner than a second edge of the second die attach pad. The first edge of the second die attach pad is opposite the second edge of the second die attach pad.

公开(公告)号：US20210116407A1

公开(公告)日：2021-04-22

申请号：US17137251

申请日：2020-12-29

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer ,  Vikas Gupta

IPC: G01N27/22 ,  H01L21/768 ,  H01L23/522 ,  H01L23/00

Abstract: Described examples include a sensor device having at least one conductive elongated first pillar positioned on a central pad of a first conductor layer over a semiconductor substrate, the first pillar extending in a first direction normal to a plane of a surface of the first conductor layer. Conductive elongated second pillars are positioned in normal orientation on a second conductor layer over the semiconductor substrate, the conductive elongated second pillars at locations coincident to via openings in the first conductor layer. The second conductor layer is parallel to and spaced from the first conductor layer by at least an insulator layer, the conductive elongated second pillars extending in the first direction through a respective one of the via openings. The at least one conductive elongated first pillar is spaced from surrounding conductive elongated second pillars by gaps.