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公开(公告)号：US20240377945A1
公开(公告)日：2024-11-14
申请号：US18214286
申请日：2023-06-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tong Zhang , Zongwang Li , Da Zhang , Rekha Pitchumani , Yang Seok Ki
IPC: G06F3/06
Abstract: Systems and methods for cache management of a storage device are disclosed. The storage device is configured to receive a first code provided by a computing device; execute the first code; perform a first update of the first storage medium based on the first code; receive a second code provided by the computing device; execute the second code; and perform a second update of the first storage medium based on the second code.
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公开(公告)号：US12105629B2
公开(公告)日：2024-10-01
申请号：US17890604
申请日：2022-08-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Zongwang Li , Sahand Salamat , Rekha Pitchumani
IPC: G06F12/0817 , G06F12/14
CPC classification number: G06F12/0828 , G06F12/1458
Abstract: Provided is a method of data storage, the method including receiving, from an application, a request to access data stored on a storage device, identifying a data access pattern of the application, and storing the data in a cache of the storage device based on the data access pattern.
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公开(公告)号：US20240303204A1
公开(公告)日：2024-09-12
申请号：US18203909
申请日：2023-05-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sahand Salamat , Zongwang Li , Rekha Pitchumani
IPC: G06F12/128 , G06F12/0864
CPC classification number: G06F12/128 , G06F12/0864 , G06F2212/1021 , G06F2212/6012
Abstract: Systems and methods for a storage system are disclosed. The storage system includes a first storage medium, a processor configured to communicate with the first storage medium, and a memory coupled to the processor. The memory stores instructions that, when executed by the processor, cause the processor to: receive a request for accessing data; search the first storage medium based on the request; receive a command from a computing device, the command including a configuration parameter; and based on the command, modify architecture of the first storage medium from a first architecture to a second architecture corresponding to the configuration parameter.
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公开(公告)号：US11940875B2
公开(公告)日：2024-03-26
申请号：US17948216
申请日：2022-09-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Rekha Pitchumani , Yang Seok Ki
CPC classification number: G06F11/1076 , G06F3/0619 , G06F3/064 , G06F3/0673
Abstract: According to one general aspect, an apparatus may include a regeneration-code-aware (RCA) storage device configured to calculate at least one type of data regeneration code for data error correction. The RCA storage device may include a memory configured to store data in chunks which, in turn, comprise data blocks. The RCA storage device may include a processor configured to compute, when requested by an external host device, a data regeneration code based upon a selected number of data blocks. The RCA storage device may include an external interface configured to transmit the data regeneration code to the external host device.
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公开(公告)号：US11928336B2
公开(公告)日：2024-03-12
申请号：US17900830
申请日：2022-08-31
Inventor： Sudarsun Kannan , Yujie Ren , Rekha Pitchumani , David Domingo
CPC classification number: G06F3/0613 , G06F3/0643 , G06F3/0667 , G06F3/0685 , G06F16/134
Abstract: Systems and methods for managing a storage system are disclosed. The storage system includes a first storage device and a second storage device different from the first storage device. A first storage operation is received for a first portion of a file, and a data structure associated with the file is identified. Based on the data structure, the first storage device is identified for the first portion of the file. The first storage operation is transmitted to the first storage device. In response to the first storage operation, the first storage device updates or accesses the first portion of the file.
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Patent Agency Ranking
公开(公告)号：US11899589B2
公开(公告)日：2024-02-13
申请号：US17500927
申请日：2021-10-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Armin Haj Aboutalebi , Rekha Pitchumani , Zongwang Li , Marie Mai Nguyen
IPC: G06F12/0882 , G06F12/02 , G06F13/16 , G06N20/00 , G06F18/214
CPC classification number: G06F12/0882 , G06F12/0238 , G06F13/1621 , G06F13/1668 , G06F18/214 , G06N20/00 , G06F2212/621
Abstract: A method for managing a memory system may include monitoring one or more accesses of a page of memory, determining, based on the monitoring, an access pattern of the page of memory, and selecting, based on the access pattern, a coherency bias for the page of memory. The monitoring may include maintaining an indication of the one or more accesses. The determining may include comparing the indication to a threshold. Maintaining the indication may include changing the indication in a first manner based on an access of the page of memory by a first apparatus. Maintaining the indication may include changing the indication in a second manner based on an access of the page of memory by a second apparatus. The first manner may counteract the second manner.
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公开(公告)号：US20230280905A1
公开(公告)日：2023-09-07
申请号：US17900830
申请日：2022-08-31
Inventor： Sudarsun Kannan , Yujie Ren , Rekha Pitchumani , David Domingo
CPC classification number: G06F3/0613 , G06F3/0667 , G06F3/0643 , G06F16/134 , G06F3/0685
Abstract: Systems and methods for managing a storage system are disclosed. The storage system includes a first storage device and a second storage device different from the first storage device. A first storage operation is received for a first portion of a file, and a data structure associated with the file is identified. Based on the data structure, the first storage device is identified for the first portion of the file. The first storage operation is transmitted to the first storage device. In response to the first storage operation, the first storage device updates or accesses the first portion of the file.
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公开(公告)号：US11726876B2
公开(公告)日：2023-08-15
申请号：US17367315
申请日：2021-07-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Mian Qin , Joo Hwan Lee , Rekha Pitchumani , Yang Seok Ki
CPC classification number: G06F11/1076 , G06F13/28
Abstract: According to one general aspect, an apparatus may include a host interface circuit configured to receive offloading instructions from a host processing device, wherein the offloading instructions instruct the apparatus to compute an error correction code associated with a plurality of data elements. The apparatus may include a memory interface circuit configured to receive the plurality of data elements. The apparatus may include a plurality of memory buffer circuits configured to temporarily store the plurality of data elements. The apparatus may include a plurality of error code computation circuits configured to, at least in part, compute the error correction code without additional processing by the host processing device.
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公开(公告)号：US11429279B2
公开(公告)日：2022-08-30
申请号：US17120098
申请日：2020-12-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jingpei Yang , Jing Yang , Rekha Pitchumani
IPC: G06F3/06 , G06F12/06 , G06F16/174
Abstract: A storage device is disclosed. The storage device may include storage for data. A host interface logic may receive a dataset and a logical address from a host. A stream assignment logic may assign a stream identifier (ID) to a compressed dataset based on a compression characteristic of the compressed dataset. The stream ID may be one of at least two stream IDs; the compressed dataset may be determined based on the dataset. A logical-to-physical translation layer may map the logical address to a physical address in the storage. A controller may store the compressed dataset at the physical address using the stream ID.
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公开(公告)号：US11061772B2
公开(公告)日：2021-07-13
申请号：US16271777
申请日：2019-02-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Mian Qin , Joo Hwan Lee , Rekha Pitchumani , Yang Seok Ki
Abstract: According to one general aspect, an apparatus may include a host interface circuit configured to receive offloading instructions from a host processing device, wherein the offloading instructions instruct the apparatus to compute an error correction code associated with a plurality of data elements. The apparatus may include a memory interface circuit configured to receive the plurality of data elements. The apparatus may include a plurality of memory buffer circuits configured to temporarily store the plurality of data elements. The apparatus may include a plurality of error code computation circuits configured to, at least in part, compute the error correction code without additional processing by the host processing device.
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