公开(公告)号：US08611144B2

公开(公告)日：2013-12-17

申请号：US13667187

申请日：2012-11-02

Applicant: QUALCOMM Incorporated

Inventor： Esin Terzioglu

IPC: G11C11/00

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: Read and write operations of a non-volatile memory (NVM) bitcell have different optimum parameters resulting in a conflict during design of the NVM bitcell. A single bitline in the NVM bitcell prevents optimum read performance. Read performance may be improved by splitting the read path and the write path in a NVM bitcell between two bitlines. A read bitline of the NVM bitcell has a low capacitance for improved read operation speed and decreased power consumption. A write bitline of the NVM bitcell has a low resistance to handle large currents present during write operations. A memory element of the NVM bitcell may be a fuse, anti-fuse, eFUSE, or magnetic tunnel junction. Read performance may be further enhanced with differential sensing read operations.

Abstract translation: 非易失性存储器（NVM）位单元的读写操作具有不同的最佳参数，从而在NVM位单元的设计过程中产生冲突。 NVM位单元中的单个位线阻止了最佳的读取性能。 通过将读路径和写入路径分割在两个位线之间的NVM位单元中可以提高读取性能。 NVM位单元的读取位线具有低电容，从而提高读取操作速度并降低功耗。 NVM位单元的写位线具有低电阻以处理写操作期间存在的大电流。 NVM位单元的存储元件可以是保险丝，反熔丝，eFUSE或磁性隧道结。 差分感测读取操作可以进一步增强读取性能。