公开(公告)号：US12035589B2

公开(公告)日：2024-07-09

申请号：US17507590

申请日：2021-10-21

Applicant: BOE Technology Group Co., Ltd.

Inventor： Can Zheng ,  Libin Liu ,  Shiming Shi ,  Zewen Bo

IPC: H10K59/131 ,  H10K59/40

CPC classification number: H10K59/131 ,  H10K59/40

Abstract: The present disclosure discloses a display substrate and a display device. The display substrate comprises: a display area, a binding area, and a fan-out area located between the display area and the binding area, the fan-out area comprises a touch control lead wire, a data lead wire, and at least one shielded wire located between the touch control lead wire and the data lead wire, and the at least one shielded wire is grounded or connected to a fixed potential.

公开(公告)号：US12008943B2

公开(公告)日：2024-06-11

申请号：US17594771

申请日：2020-10-30

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Tian Dong ,  Can Zheng ,  Li Wang ,  Long Han ,  Yu Feng ,  Hao Zhang ,  Jiangnan Lu ,  Jie Zhang ,  Bo Wang ,  Jingquan Wang

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G2310/0297 ,  G09G2310/061

Abstract: The display panel includes a plurality of rows and a plurality of columns of pixel circuits, a plurality of rows of gate lines, a plurality rows of reset control lines, and a plurality of columns of data lines, a same row of pixel circuits corresponds to two rows of gate lines, and one/the other row of gate line is electrically connected to odd/even-numbered columns of pixel circuits in the row of pixel circuits, and provides a corresponding gate driving signal for the odd/even-numbered columns of pixel circuits; a same column of pixel circuits corresponds to two columns of data lines, and one/the other column of data line of the two columns of data lines is electrically connected to odd/even-numbered rows of pixel circuits, and provides a corresponding data voltage for the odd/even-numbered rows of pixel circuits.

公开(公告)号：US11997899B2

公开(公告)日：2024-05-28

申请号：US17785662

申请日：2021-08-11

Applicant: BOE Technology Group Co., Ltd.

Inventor： Can Zheng ,  Lujiang Huangfu ,  Libin Liu ,  Shiming Shi

IPC: G09G3/3233 ,  G09G3/3266 ,  G09G3/3291 ,  H10K59/121 ,  H10K59/131 ,  H10K59/12

CPC classification number: H10K59/131 ,  G09G3/3233 ,  G09G3/3266 ,  G09G3/3291 ,  H10K59/1213 ,  H10K59/1216 ,  G09G2300/0852 ,  G09G2310/0278 ,  G09G2310/061 ,  G09G2320/0233 ,  H10K59/1201

Abstract: The present disclosure provides a pixel circuit, a pixel driving method, a display panel and a display device. The pixel circuit includes a light-emitting element, a driving circuitry, a first energy storage circuitry, a second energy storage circuitry, a data writing circuitry and a compensation circuitry. The data writing circuitry is configured to write a data voltage into a first end of the first energy storage circuitry under the control of a gate driving signal provided by a gate line. The compensation circuitry is configured to control a control end of the driving circuitry to be electrically coupled to a second end of the driving circuitry under the control of a compensation control signal. The driving circuitry is configured to generate a driving current for driving the light-emitting element under the control of a potential at its control end.

公开(公告)号：US11984084B2

公开(公告)日：2024-05-14

申请号：US17414600

申请日：2020-12-29

Applicant: BOE Technology Group Co., Ltd.

Inventor： Can Zheng ,  Libin Liu

IPC: G09G3/3266 ,  G09G3/36 ,  G11C19/28

CPC classification number: G09G3/3266 ,  G09G3/3677 ,  G11C19/28 ,  G09G2300/0408 ,  G09G2310/0286 ,  G09G2320/0247 ,  G09G2320/064

Abstract: The disclosure relates to a shift register, a driving method thereof, a gate drive circuit, and a display device. An output pulse width can be reduced by 1/(n+1) to (n−1)/(n+1) clock cycle by setting a pulse width modulation module (104), where n is the number of clock signal terminals in one-to-one correspondence with the enable signal terminals, and the pulse width reduced by 1/(n+1) to (n−1)/(n+1) clock cycle needs to be output several times under the condition that the light emitting duration of pixels is unchanged. In this way, the refresh rate is increased, and thus the flicker phenomenon in the process of low gray-scale brightness adjustment is less detectable to the human eyes.

公开(公告)号：US11908404B2

公开(公告)日：2024-02-20

申请号：US17599387

申请日：2021-01-14

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Lujiang Huangfu ,  Libin Liu ,  Can Zheng

IPC: G09G3/3233

CPC classification number: G09G3/3233 ,  G09G2300/0842 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2330/02

Abstract: The present disclosure provides a display panel, a pixel circuit and a method for driving the pixel circuit, the pixel circuit includes: a storage capacitor circuit; a light-emitting element; a driving transistor; a reset circuit, the reset circuit is configured to receive a reset control signal and reset a first node and a second node according to the reset control signal, or receive a writing control signal and/or a timing sequence control signal of an adjacent pixel row and reset the first node and the second node according to the writing control signal and/or the timing sequence control signal of the adjacent pixel row; a threshold compensation circuit, configured to receive a compensation control signal and write a compensation voltage into the first node according to the compensation control signal; a writing circuit; and a light-emitting control circuit.

公开(公告)号：US11893938B2

公开(公告)日：2024-02-06

申请号：US17912090

申请日：2021-02-09

Applicant: BOE Technology Group Co., Ltd.

Inventor： Li Wang ,  Can Zheng

IPC: G09G3/3233 ,  H10K59/131

CPC classification number: G09G3/3233 ,  H10K59/131 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2310/0202 ,  G09G2320/0247 ,  G09G2360/16

Abstract: Provided are a pixel circuit, a display panel and a display apparatus. The pixel circuit includes: a first resetting switching transistor, a first data writing switching transistor, a storage capacitor, a first compensation capacitor, a second compensation capacitor, and a driving transistor; the first resetting switching transistor includes a first switching sub-transistor and a second switching sub-transistor connected in series, and the first data writing switching transistor includes a third switching sub-transistor and a fourth switching sub-transistor connected in series. The first compensation capacitor and the second compensation capacitor are used to enable a voltage Vn1′ of the first node to be smaller than a voltage Vn3′ of the third node and larger than a voltage Vn4′ of the fourth node in a light-emitting stage.

公开(公告)号：USRE49782E1

公开(公告)日：2024-01-02

申请号：US17191101

申请日：2021-03-03

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Can Zheng

IPC: G09G3/36 ,  G11C19/28

CPC classification number: G09G3/3677 ,  G09G3/36 ,  G11C19/28 ,  G09G2310/0286 ,  G09G2310/06

Abstract: A shift register includes: an input unit, configured to provide an input signal to a first node; a pull-up unit, configured to provide a voltage of a first supply voltage terminal to an output terminal; a pull-up control unit, configured to provide the voltage of the first supply voltage terminal or a voltage of a second supply voltage terminal to a second node; a pull-down unit, configured to provide a third clock signal from a third clock signal terminal to the output terminal; a pull-down control unit, configured to provide the voltage of the first supply voltage terminal to the first node; a first noise reduction unit, configured to reduce electrical leakage of the input unit to the first node; and a second noise reduction unit, configured to reduce electrical leakage of the pull-down control unit to the first node.

公开(公告)号：US11854460B2

公开(公告)日：2023-12-26

申请号：US18092974

申请日：2023-01-04

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Can Zheng

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G2310/0286

Abstract: A shift register unit, a driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a first input circuit, a second input circuit, an output circuit, a first control circuit, and a second control circuit. The first input circuit is electrically connected to a first node, and is configured to transmit an input signal to the first node; the second input circuit is electrically connected to the first node and a second node, and is configured to control a level of the second node; the first control circuit is electrically connected to the second node and a third node, and is configured to control a level of the third node; and the output circuit is electrically connected to the third node and an output terminal, and is configured to output an output signal to the output terminal.

公开(公告)号：US11790850B2

公开(公告)日：2023-10-17

申请号：US17791965

申请日：2021-05-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Lujiang Huangfu ,  Li Wang ,  Can Zheng ,  Libin Liu

IPC: G09G3/3258

CPC classification number: G09G3/3258 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2310/0286 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2320/0233 ,  G09G2320/0247

Abstract: A pixel driving circuit includes a reset sub-circuit, a compensation sub-circuit, a light-emitting control sub-circuit and a driving sub-circuit. The reset sub-circuit is configured to transmit an initialization signal received from an initialization signal terminal to the light-emitting control sub-circuit. The light-emitting control sub-circuit is configured to transmit the initialization signal to the first node. The compensation sub-circuit is configured to transmit the initialization signal from the first node to a second node so as to reset a voltage of the second node. The driving sub-circuit is configured to open a conductive path from a first voltage signal terminal to the initialization signal terminal during a process of resetting the voltage of the second node.

公开(公告)号：US11094239B2

公开(公告)日：2021-08-17

申请号：US16622099

申请日：2019-01-25

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Can Zheng

IPC: G09G3/20 ,  G11C19/18 ,  G11C19/28

Abstract: A shift register and driving method thereof, a gate driving circuit and a display device are provided. The shift register includes a first input unit, a second input unit, a pull-up control unit, a pull-down control unit, an output control unit and an output reset unit, wherein the first input unit, the second input unit, the pull-up control unit, the pull-down control unit and the output control unit are coupled to a first node, and the pull-up control unit, the pull-down control unit and the output reset unit are coupled to a second node.