公开(公告)号：US10761988B2

公开(公告)日：2020-09-01

申请号：US16142330

申请日：2018-09-26

Applicant: Arm Limited

Inventor： Radhika Sanjeev Jagtap ,  Nikos Nikoleris ,  Andreas Lars Sandberg ,  Stephan Diestelhorst

IPC: G06F12/0864 ,  G06F12/1045

Abstract: Aspects of the present disclosure relate to an apparatus comprising a data array having locality-dependent latency characteristics such that an access to an open unit of the data array has a lower latency than an access to a closed unit of the data array. Set associative cache indexing circuitry determines, in response to a request for data associated with a target address, a cache set index. Mapping circuitry identifies, in response to the index, a set of data array locations corresponding to the index, according to a mapping in which a given unit of the data array comprises locations corresponding to a plurality of consecutive indices, and at least two locations of the set of locations corresponding to the same index are in different units of the data array. Cache access circuitry accesses said data from one of the set of data array locations.

公开(公告)号：US10712965B2

公开(公告)日：2020-07-14

申请号：US15806580

申请日：2017-11-08

Applicant: ARM LIMITED

Inventor： Andreas Lars Sandberg ,  Nikos Nikoleris ,  David Hennah Mansell

IPC: G06F3/06 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1009 ,  G06F12/0831

Abstract: An apparatus and method are provided for transferring data between address ranges in memory. The apparatus comprises a data transfer controller, that is responsive to a data transfer request received by the apparatus from a processing element, to perform a transfer operation to transfer data from at least one source address range in memory to at least one destination address range in the memory. A redirect controller is then arranged, whilst the transfer operation is being performed, to intercept an access request that specifies a target address within a target address range, and to perform a memory redirection operation so as to cause the access request to be processed without awaiting completion of the transfer operation. Via such an approach, the apparatus can effectively hide from the source of the access request the fact that the transfer operation is in progress, and hence the transfer operation can be arranged to occur in the background, and in a manner that is transparent to the software executing on the source that has issued the access request.

公开(公告)号：US20190004960A1

公开(公告)日：2019-01-03

申请号：US16005934

申请日：2018-06-12

Applicant: ARM Limited

Inventor： Wei Wang ,  Stephan Diestelhorst ,  Wendy Arnott ELSASSER ,  Andreas Lars Sandberg ,  Nikos NIKOLERIS

IPC: G06F12/0873 ,  G06F12/0871 ,  G06F12/02 ,  G06F12/0895 ,  G06F1/32

Abstract: An apparatus and method are provided for handling caching of persistent data. The apparatus comprises cache storage having a plurality of entries to cache data items associated with memory address in a non-volatile memory. The data items may comprise persistent data items and non-persistent data items. Write back control circuitry is used to control write back of the data items from the cache storage to the non-volatile memory. In addition, cache usage determination circuitry is used to determine, in dependence on information indicative of capacity of a backup energy source, a subset of the plurality of entries to be used to store persistent data items. In response to an event causing the backup energy source to be used, the write back control circuitry is then arranged to initiate write back to the non-volatile memory of the persistent data items cached in the subset of the plurality of entries. By constraining the extent to which the cache storage is allowed to store persistent data items, taking into account the capacity of the backup energy source, the persistence of those data items can then be guaranteed in the event of the backup energy source being triggered, for example due to removal of the primary energy source for the apparatus.