公开(公告)号：US20200183736A1

公开(公告)日：2020-06-11

申请号：US16210231

申请日：2018-12-05

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Brett S. Feero ,  Nikhil Gupta

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0815

Abstract: In an embodiment, at least one CPU processor and at least one coprocessor are included in a system. The CPU processor may issue operations to the coprocessor to perform, including load/store operations. The CPU processor may generate the addresses that are accessed by the coprocessor load/store operations, as well as executing its own CPU load/store operations. The CPU processor may include a memory ordering table configured to track at least one memory region within which there are outstanding coprocessor load/store memory operations that have not yet completed. The CPU processor may delay CPU load/store operations until the outstanding coprocessor load/store operations are complete. In this fashion, the proper ordering of CPU load/store operations and coprocessor load/store operations may be maintained.

公开(公告)号：US10133571B1

公开(公告)日：2018-11-20

申请号：US15171369

申请日：2016-06-02

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Mridul Agarwal ,  Pradeep Kanapathipillai ,  Sean M. Reynolds

IPC: G06F9/30 ,  G06F9/38

Abstract: A load-store unit having one or more banked queues is disclosed. In one embodiment, a load-store unit includes at least one queue that is subdivided into multiple banks. Although divided into multiple banks, the queue logically appears to software as a single queue. A first bank of the queue includes a first plurality of entries, with the second bank of the queue having a second plurality of entries, wherein each of the entries is arranged to store memory instructions. Each of the banks is associated with corresponding logic circuitry that controls one or more pointers for that bank. The pointer information may be exchanged between the logic circuits associated with the banks. Based on the pointer information that is exchanged, each bank may output (e.g., for retirement) one entry per cycle.