-
公开(公告)号：US07913034B2
公开(公告)日：2011-03-22
申请号：US11832220
申请日：2007-08-01
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth available for the read and the write operations by avoiding consecutive accesses to the same memory bank and by minimizing dead cycles. The arbiter first divides DRAM accesses into write accesses and read accesses. The access requests are divided into accesses per memory bank with a threshold limit imposed on the number of accesses to each memory bank. The write receive packets are rotated among the banks based on the write queue status. The status of the write queue for each memory bank may also be used for system flow control. The arbiter also typically includes the ability to determine access windows based on the status of the command queues, and to perform arbitration on each access window.
摘要翻译： 访问仲裁器被用于将对DRAM存储器件，特别是快速循环DRAM中的各个存储体的读取和写入访问请求进行优先级排序。 这用于通过避免对同一存储体的连续访问并且通过最小化死循环来优化用于读取和写入操作的存储器带宽。 仲裁器首先将DRAM访问划分为写访问和读访问。 访问请求被划分为每个存储体的访问，并且对每个存储体的访问次数施加了阈值限制。 基于写入队列状态，写入接收数据包在存储体之间旋转。 每个存储体的写入队列的状态也可以用于系统流控制。 仲裁器还通常包括基于命令队列的状态来确定访问窗口的能力，并且在每个访问窗口上执行仲裁。
-
公开(公告)号：US20090175275A1
公开(公告)日：2009-07-09
申请号：US12348938
申请日：2009-01-06
IPC分类号： H04L12/56
CPC分类号： H04L47/527 , H04L47/50 , H04L47/522 , H04L47/568 , H04L47/58
摘要： A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.
摘要翻译： 提供了一种用于灵活数据流的网络处理器数据流芯片和方法。 数据流芯片包括多个片上数据传输和调度电路结构。 响应于指标选择数据传输和调度电路结构。 数据传输电路结构可以包括可选择的帧处理和数据传输功能。 可选择的帧处理可以包括剪切和粘贴，完全调度和存储和调度帧处理。 调度功能包括完整的内部调度，与外部调度器进行通信的日历调度以及外部日历调度。 在本发明的另一方面，数据传输功能可以包括用于选择性地提供对数据流芯片资源的特权访问的低延迟和正常等待时间的外部处理器接口。
-
公开(公告)号：US07522621B2
公开(公告)日：2009-04-21
申请号：US11030344
申请日：2005-01-06
IPC分类号： H04L12/56
CPC分类号： H04L49/901 , H04L49/90 , H04L49/9021
摘要： Apparatus and method for storing network frame data which is to be modified. A plurality of buffers stores the network data which is arranged in a data structure identified by a frame control block and buffer control block. A plurality of buffer control blocks associated with each buffer storing the frame data establishes a sequence of the buffers. Each buffer control block has data for identifying a subsequent buffer within the sequence. The first buffer is identified by a field of a frame control block as well as the beginning and ending address of the frame data. The frame data can be modified without rewriting the data to memory by altering the buffer control block and/or frame control block contents without having to copy or rewrite the data in order to modify it.
摘要翻译： 用于存储要修改的网络帧数据的装置和方法。 多个缓冲器存储布置在由帧控制块和缓冲器控制块所标识的数据结构中的网络数据。 与存储帧数据的每个缓冲器相关联的多个缓冲器控制块建立缓冲器的序列。 每个缓冲器控制块具有用于识别序列内的后续缓冲器的数据。 第一缓冲器由帧控制块的字段以及帧数据的开始和结束地址来标识。 可以通过改变缓冲器控制块和/或帧控制块内容而不将数据重写到存储器来修改帧数据，而不必复制或重写数据以便修改它。
-
34.发明申请STRUCTURE AND METHOD FOR SCHEDULER PIPELINE DESIGN FOR HIERARCHICAL LINK SHARING 失效用于分层链路共享的调度器管道设计的结构和方法公开(公告)号：US20080298372A1
公开(公告)日：2008-12-04
申请号：US12175479
申请日：2008-07-18
IPC分类号： H04L12/56
摘要： A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.
摘要翻译： 描述了用于网络流量管理中的流水线配置，用于以分层链接排列的事件的硬件调度。 该配置通过最小化外部SRAM存储器件的使用来降低成本。 这导致一些外部存储器设备被不同类型的控制块共享，例如流队列控制块，帧控制块和层次控制块。 使用SRAM和DRAM存储器件，这取决于控制块的内容（仅读取 - 修改 - 写入或仅读取）在排队和出队，或仅读出 - 修改 - 写出。 调度器在出口日历设计中使用基于时间的日历和加权公平排队日历。 不频繁访问的控制块存储在DRAM存储器中，而频繁访问的控制块存储在SRAM中。
-
35.发明授权Apparatus, method and program product to generate and use CRC in communications network 有权在通信网络中生成和使用CRC的装置，方法和程序产品公开(公告)号：US07336667B2
公开(公告)日：2008-02-26
申请号：US10301247
申请日：2002-11-21
CPC分类号： H04L1/0061 , H04L1/0072 , H04L12/5601 , H04L45/742 , H04L2012/5627 , H04L2012/5656
摘要： The CRC for the CPS Header of an ATM AAL2 cell is generated by a CRC generator which uses the 8 bits of the CID field to generate partial 5 bits CRCs which are loaded in a first table. The 6 bits LI field and 5 bits UUI field are added to the partial 5 bits CRC to form 16 bits. The CRC generator uses the 216 bits to generate a second CRC table. The CRC for a particular CPS header is generated by correlating bits in the CID field, Li field and UUI field with the two tables.
摘要翻译： 用于ATM AAL2单元的CPS头的CRC由CRC发生器产生，CRC发生器使用CID字段的8位来产生加载在第一表中的部分5位CRC。 6位LI字段和5位UUI字段被添加到部分5位CRC以形成16位。 CRC发生器使用2位16位产生第二个CRC表。 通过将CID字段，Li字段和UUI字段中的比特与两个表相关来生成特定CPS头的CRC。
-
36.发明授权Apparatus and method for efficiently sharing memory bandwidth in a network processor 失效在网络处理器中有效共享存储器带宽的装置和方法公开(公告)号：US06757795B2
公开(公告)日：2004-06-29
申请号：US10068392
申请日：2002-02-05
申请人： Peter I. A. Barri , Jean L. Calvignac , Marco C. Heddes , Joseph F. Logan , Alex M. M. Niemegeers , Fabrice J. Verplanken , Miroslav Vrana
发明人： Peter I. A. Barri , Jean L. Calvignac , Marco C. Heddes , Joseph F. Logan , Alex M. M. Niemegeers , Fabrice J. Verplanken , Miroslav Vrana
IPC分类号： G05F1200
CPC分类号： G06F13/18 , G06F13/161
摘要： A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.
摘要翻译： 网络处理器（NP）包括允许最大限度利用存储器的控制器。 控制器包括一个内存仲裁器，用于监视NP中请求者的内存访问请求，并授予高优先级请求者每次访问存储器所请求的所有内存带宽。 如果高优先级请求者请求的存储器带宽小于全部存储器带宽，则请求的带宽和全部存储器带宽之间的差异被分配给较低优先权请求者。 通过这样做，每个存储器访问都利用了完整的存储器带宽。
-
公开(公告)号：US6044079A
公开(公告)日：2000-03-28
申请号：US943606
申请日：1997-10-03
CPC分类号： H04L12/5601 , H04L49/309 , H04L2012/5647 , H04L2012/5654
摘要： The present invention is an apparatus that manages Packet-Discard at a switch in an ATM network. The apparatus includes a table having a number of table addresses (or indexes). Each table address stores a record for incoming data cells of a frame. The records indicate whether data cells of the frame are be discarded. The number of possible cell identifiers is greater than the number of table addresses. The apparatus also includes a processor unit which receives a data cell having a cell identifier. The processor unit determines a table key, based on the cell identifier such that the table key is within the range of the table addresses. The processor unit then searches a record in the table associated with the table key to determine whether the data cell is to be discarded.
摘要翻译： 本发明是一种在ATM网络中的交换机处理Packet-Discard的装置。 该装置包括具有多个表地址（或索引）的表。 每个表地址存储帧的传入数据单元的记录。 记录表示帧的数据单元是否被丢弃。 可能的小区标识符的数量大于表地址的数量。 该装置还包括接收具有小区标识符的数据小区的处理器单元。 处理器单元基于小区标识符来确定表密钥，使得表密钥在表地址的范围内。 处理器单元然后搜索与表键相关联的表中的记录，以确定数据单元是否被丢弃。
-
公开(公告)号：US08867395B2
公开(公告)日：2014-10-21
申请号：US13570343
申请日：2012-08-09
IPC分类号： H04L12/741 , G06F9/38 , H04L12/801
CPC分类号： G06F9/3885 , H04L45/74 , H04L47/10
摘要： Mechanisms are provided for a network processor comprising a parser, the parser being operable to work in normal operation mode or in repeat operation mode, the parser in normal operation mode loading and executing at least one rule in a first and a second working cycle respectively, the parser in repeat operation mode being operable to repeatedly execute a repeat-instruction, the execution of each repeat corresponding to one working cycle.
-
公开(公告)号：US07929438B2
公开(公告)日：2011-04-19
申请号：US12175479
申请日：2008-07-18
IPC分类号： H04J1/16
摘要： A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.
摘要翻译： 描述了用于网络流量管理中的流水线配置，用于以分层链接排列的事件的硬件调度。 该配置通过最小化外部SRAM存储器件的使用来降低成本。 这导致一些外部存储器设备被不同类型的控制块共享，例如流队列控制块，帧控制块和层次控制块。 使用SRAM和DRAM存储器件，这取决于控制块的内容（仅读取 - 修改 - 写入或仅读取）在排队和出队，或仅读出 - 修改 - 写出。 调度器在出口日历设计中使用基于时间的日历和加权公平排队日历。 不频繁访问的控制块存储在DRAM存储器中，而频繁访问的控制块存储在SRAM中。
-
40.发明授权公开(公告)号：US07457241B2
公开(公告)日：2008-11-25
申请号：US10772737
申请日：2004-02-05
IPC分类号： H04J1/16
摘要： A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.
摘要翻译： 描述了用于网络流量管理中的流水线配置，用于以分层链接排列的事件的硬件调度。 该配置通过最小化外部SRAM存储器件的使用来降低成本。 这导致一些外部存储器设备被不同类型的控制块共享，例如流队列控制块，帧控制块和层次控制块。 使用SRAM和DRAM存储器件，这取决于控制块的内容（仅读取 - 修改 - 写入或仅读取）在排队和出队，或仅读出 - 修改 - 写出。 调度器在出口日历设计中使用基于时间的日历和加权公平排队日历。 不频繁访问的控制块存储在DRAM存储器中，而频繁访问的控制块存储在SRAM中。
-
-
-
-
-
-
-
-
-
搜索结果
41 条记录 (耗时 0.029 秒)
